3D semiconductor device, fabrication method and system
A 3D memory device, the device including: a first single crystal layer including memory peripheral circuits; a first memory layer including a first junction-less transistor; a second memory layer including a second junction-less transistor; and a third memory layer including a third junction-less transistor, where the first memory layer overlays the first single crystal layer, where the second memory layer overlays the first memory layer, where the third memory layer overlays the second memory layer, where the first junction-less transistor, the second junction-less transistor and the third junction-less transistor are formed by a single lithography and etch process, and where the first memory layer includes a nonvolatile NAND type memory.
1. A method for fabrication of a 3D semiconductor device, the method comprising:
providing a substrate comprising a single crystal layer;
forming a plurality of first transistors in and on said single crystal layer; then
forming at least one metal layer, said at least one metal layer comprising connections between said first transistors,
wherein a portion of said at least one metal layer comprising said connections between said first transistors form memory peripheral circuits, said peripheral circuits comprise decoder circuits; then
forming a stack of at least sixteen layers,
wherein said stack of at least sixteen layers comprises odd numbered layers and even numbered layers,
wherein said odd numbered layers comprise a first material and said even numbered layers comprise a second material,
wherein said first material is of a different composition than said second material, and
wherein said forming said stack is performed as part of forming a multilevel memory structure; and then
processing said stack of at least sixteen layers forming at least eight layers of memory cells,
wherein said at least eight layers of memory cells are controlled by said periphery circuits,
wherein at least said forming said stack of at least sixteen layers and said processing said stack of at least sixteen layers comprise forming a staircase structure,
wherein said staircase structure comprises a portion of connection paths from said peripheral circuits to at least one of said memory cells,
wherein at least one of said memory cells overlays said peripheral circuits,
wherein each of said memory cells comprises at least one second transistor, said second transistor comprises a source, channel, and drain, and
wherein said source, said channel, and said drain comprise similar doping.
2. The method according to claim 1 ,
wherein said processing said stack of at least sixteen layers comprises annealing of said first transistors.
3. The method according to claim 1 ,
wherein said processing said stack of at least sixteen layers comprises forming metal layers as part of forming connections between said peripheral circuits and said memory cells.
4. The method according to claim 1 ,
wherein said memory cells are part of a non-volatile NAND memory.
5. The method according to claim 1 ,
wherein said memory cells are arranged as memory arrays, and
wherein transport of control signals to said memory cells and said memory arrays comprise a plurality of word-lines and a plurality of bit-lines.
6. The method according to claim 1 ,
wherein said processing said stack of at least sixteen layers comprises Atomic Layer Deposition (ALD).
7. The method according to claim 1 , further comprising:
a first set of external connections underlying said single crystal layer to connect said device to a first external device; and
a second set of external connections overlying said at least eight layers of memory cells to connect said device to a second external device,
wherein said first set of external connections comprises a through silicon via (TSV).
8. A method for fabrication of a 3D semiconductor device, the method comprising:
providing a substrate comprising a single crystal layer;
forming a plurality of first transistors in and on said single crystal layer; then
forming at least one metal layer, said at least one metal layer comprising connections between said first transistors,
wherein a portion of said at least one metal layer comprising said connections between said first transistors form memory peripheral circuits, said peripheral circuits comprise decoder circuits; then
forming a stack of at least sixteen layers,
wherein said stack of at least sixteen layers comprises odd numbered layers and even numbered layers,
wherein said odd numbered layers comprise a first material and said even numbered layers comprise a second material,
wherein said first material is of a different composition than said second material, and
wherein said forming said stack is performed as part of forming a multilevel memory structure; and then
processing said stack of at least sixteen layers forming at least eight layers of memory cells,
wherein said at least eight layers of memory cells are controlled by said periphery circuits,
wherein at least said forming said stack of at least sixteen layers and said processing said stack of at least sixteen layers comprise forming a staircase structure,
wherein said staircase structure comprises a portion of connection paths from said peripheral circuits to at least one of said memory cells,
wherein at least one of said memory cells overlays said peripheral circuits.
9. The method according to claim 8 ,
wherein said processing said stack of at least sixteen layers comprises annealing of said first transistors.
10. The method according to claim 8 ,
wherein each of said memory cells comprises at least one second transistor, said second transistor comprises a source, channel, and drain, and
wherein said source, said channel, and said drain comprise similar doping.
11. The method according to claim 8 ,
wherein said processing said stack of at least sixteen layers comprises forming metal layers as part of forming connections between said periphery circuits and said memory cells.
12. The method according to claim 8 ,
wherein said memory cells are part of a non-volatile NAND memory.
13. The method according to claim 8 ,
wherein said processing said stack of at least sixteen layers comprises use of Atomic Layer Deposition (ALD).
14. The method according to claim 8 , further comprising:
forming a first set of external connections underlying said single crystal layer to connect said device to a first external device; and
forming a second set of external connections overlying said at least eight layers of memory cells to connect said device to a second external device,
wherein said first set of external connections comprises a through silicon via (TSV).
15. A method for fabrication of a 3D semiconductor device, the method comprising:
providing a substrate comprising a single crystal layer;
forming a plurality of first transistors in and on said single crystal layer; then
forming at least one metal layer, said at least one metal layer comprising connections between said first transistors,
wherein a portion of said at least one metal layer comprising said connections between said first transistors form memory peripheral circuits; then
forming a stack of at least sixteen layers,
wherein said stack of at least sixteen layers comprises odd numbered layers and even numbered layers,
wherein said odd numbered layers comprise a first material and said even numbered layers comprise a second material,
wherein said first material is of a different composition than said second material, and
wherein said forming said stack is performed as part of forming a multilevel memory structure; and then
processing said stack of at least sixteen layers forming at least eight layers of memory cells,
wherein said at least eight layers of memory cells are controlled by said periphery circuits.
16. The method according to claim 15 ,
wherein at least said forming said stack of at least sixteen layers and said processing said stack of at least sixteen layers comprise forming a staircase structure,
wherein said staircase structure comprises a portion of connection paths from said peripheral circuits to at least one of said memory cells.
17. The method according to claim 15 ,
wherein said processing said stack of at least sixteen layers comprises annealing of said first transistors.
18. The method according to claim 15 ,
wherein each of said memory cells comprises at least one second transistor, said second transistor comprises a source, channel, and drain, and
wherein said source, said channel, and said drain comprise similar doping.
19. The method according to claim 15 ,
wherein said processing said stack of at least sixteen layers comprises forming metal layers as part of forming connections between said periphery circuits and said memory cells.
20. The method according to claim 15 ,
wherein said memory cells are part of a non-volatile NAND memory.