Methods for fabrication of 3-dimensional nor memory arrays
Carbon has many advantageous uses as a sacrificial material in the fabricating thin-film storage transistors, such as those organized as NOR memory strings. In one implementation, the carbon layers are replaced by heavily doped n-type polysilicon source and drain regions at a late step during device fabrication. As a result, many high temperature steps within the fabrication process may now be carried out without concern for thermal diffusion from the heavily doped polysilicon, thus allowing phosphorus to be used as the n-type dopant.
1 . A process suitable for use in fabricating storage transistors of a NOR memory string above a planar surface of a semiconductor substrate, comprising:
above the planar surface, repeatedly depositing, alternately and one over another, a multi-layer and an isolation dielectric layer, each multilayer comprising first and second semiconductor layers, each of a first conductivity type, a carbon layer between the first and the second semiconductor layers;
cutting a plurality of trenches into the multilayers and the isolation dielectric layers, thereby (1) exposing the carbon layers, the first and the second semiconductor layers and the isolation dielectric layers at the sidewalls of the trenches, each trench having (i) a depth that extends along a first direction that is substantially normal to the planar surface, (ii) a length that extends along a second direction that is substantially parallel to the planar surface, (iii) a width that extends along a third direction that is substantially orthogonal to the depth and the length, the length of the trench being substantially greater than its width; and (2) dividing the multi-layers into a plurality of stacks of multi-layer strips, each stack being separated from an adjacent stack by the width of one of the trenches, with each multi-layer strip being the portion of a multi-layer between adjacent trenches;
filling the trenches with a dielectric filler material;
cutting a plurality of via openings in the dielectric filler material of each trench;
depositing into each via opening a charge-storage layer and a conductor;
cutting a plurality of shafts at predetermined locations into stack of multi-layer strips, thereby exposing the carbon layer of each multi-layer strip in each stack to the shaft; and
through the shafts, in place of each carbon layer of each multi-layer strip, providing a third semiconductor layer of a second conductivity type.
2 . The process of claim 1 wherein the multi-layer further comprises a first sacrificial layer in contact with the first semiconductor layer or the second semiconductor layer.
3 . The process of claim 2 , wherein the first sacrificial layer is replaced by a conductive material after the trenches are cut.
4 . The process of claim 1 , wherein the charge-storage layer comprises a tunneling layer, a charge-trapping layer and a blocking layer.
5 . The process of claim 1 , wherein the charge-storage layer comprises one or more of: silicon oxide, zirconium oxide, one or more multi-layers each comprising silicon oxide and silicon nitride, aluminum oxide, and any combination thereof.
6 . The process of claim 1 , wherein providing a third semiconductor layer of a second conductivity type in place of each carbon layer of each multi-layer strip comprises:
removing each carbon layer by an ashing step that converts the carbon layers into carbon oxide gases, which are then expelled through the shafts, thereby creating a space in place of the carbon layers; and
depositing the third semiconductor layer into the space.
7 . The process of claim 6 , wherein the third semiconductor layer comprises a conformal polysilicon liner.
8 . The process of claim 7 , further comprising filling the remainder of the space by a second dielectric filler material.
9 . The process of claim 1 , wherein the isolation dielectric layer comprises a dielectric material.
10 . The process of claim 1 , wherein the isolation dielectric layer comprises silicon oxycarbon.
11 . The process of claim 1 , wherein the trenches are cut in multiple phases wherein, in each phase, a portion of the trenches are cut and filled with the first sacrificial material.
12 . The process of claim 1 , wherein the first semiconductor layer, the second semiconductor layer, the third semiconductor layer, the charge-storage layer and the conductor provide a bit line, a source line, a channel region, a charge-storage region and a gate electrode, respectively, of a storage transistor of the NOR memory string.
13 . The process of claim 12 , wherein the storage transistors of the NOR memory string share the source line and the bit line.