Semiconductor memory device and method for biasing same
Techniques for providing a semiconductor memory device are disclosed. In one particular embodiment, the techniques may be realized as a semiconductor memory device including a plurality of memory cells arranged in an array of rows and columns. Each memory cell may include a first region coupled to a source line, a second region coupled to a bit line, and a body region capacitively coupled to at least one word line via a tunneling insulating layer and disposed between the first region and the second region.
1. A semiconductor memory device comprising:
a plurality of memory cells arranged in an array of rows and columns, each memory cell comprising:
a first region coupled to a source line;
a second region coupled to a bit line; and
a body region capacitively coupled to two distinct word lines via two respective multilayer tunneling insulating regions and disposed between the first region and the second region, wherein each of the two distinct word lines is disposed directly adjacent to its respective multilayer tunneling insulating region, wherein each of the two distinct word lines is configured to be operated independently to control access to a respective portion of the body region, and wherein the two respective multilayer tunneling insulating regions extend along respective lateral sides of the first region, the second region, and the body region beyond where the body region is capacitively coupled to the two distinct word lines;
wherein the first region, the body region, and the second region are disposed in a respective sequential contiguous relationship and extend outward from a substrate in a pillar structure.
2. The semiconductor memory device according to claim 1 , wherein the first region and the second region are doped with donor impurities.
3. The semiconductor memory device according to claim 1 , wherein the body region is doped with acceptor impurities.
4. The semiconductor memory device according to claim 1 , wherein each tunneling insulating layer comprises a plurality of insulating or dielectric layers.
5. The semiconductor memory device according to claim 4 , wherein the plurality of insulating or dielectric layers comprise at least one of a thermal oxide layer, a nitride layer, an oxide layer, a charge trapping nitride layer, and a blocking oxide layer.
6. The semiconductor memory device according to claim 5 , wherein the plurality of insulating or dielectric layers are of various thicknesses.
7. The semiconductor memory device according to claim 1 , wherein at least one word line comprises a plurality of layers.
8. The semiconductor memory device according to claim 7 wherein the plurality of layers of the word line comprise a first silicon layer having a thickness of approximately one tenth of a thickness of a second metal layer.
9. The semiconductor memory device according to claim 1 , wherein the substrate defines a plane and is coupled to an electrical ground.
10. The semiconductor memory device according to claim 1 , wherein the body region comprises a first floating body region and a second floating body region.
11. The semiconductor memory device according to claim 10 , wherein the first floating body region is capacitively coupled to a first word line of the two distinct word lines and the second floating body region is capacitively coupled to a second word line of the two distinct word lines.
12. The semiconductor memory device according to claim 1 , wherein at least one word line is capacitively coupled to a second body region.
13. The semiconductor memory device according to claim 12 , wherein the at least one word line is capacitively coupled to a first floating gate region of the body region and a second floating gate region of the second body region.
14. The semiconductor memory device according to claim 1 wherein the first region comprises a continuous planar region.
15. The semiconductor memory device according to claim 14 , wherein the first region further comprises a plurality of protrusions formed on the continuous planar region.
16. The semiconductor memory device according to claim 1 , wherein the first region comprises an elongated continuous planar region.
17. The semiconductor memory device according to claim 16 , wherein the elongated continuous planar region forms a column or a row of the array.
18. A method for biasing a semiconductor memory device comprising the steps of:
applying a plurality of voltage potentials to a plurality of memory cells arranged in an array of rows and columns, wherein applying the plurality of voltage potentials to the plurality of memory cells comprises for each memory cell:
applying a first voltage potential to a first region of the memory cell;
applying a second voltage potential to a second region of the memory cell; and
applying respective third voltage potentials to a body region of the memory cell via two distinct word lines that are capacitively coupled to the body region via two respective multilayer tunneling insulating regions, wherein each of the two distinct word lines is disposed directly adjacent to its respective multilayer tunneling insulating region, wherein each of the two distinct word lines is configured to be operated independently to control access to a respective portion of the body region, and wherein the two respective multilayer tunneling insulating regions extend along respective lateral sides of the first region, the second region, and the body region beyond where the body region is capacitively coupled to the two distinct word lines;
wherein the first region, the body region, and the second region are disposed in a respective sequential contiguous relationship and extend outward from a substrate in a pillar structure.
19. The method according to claim 18 , further comprising coupling the substrate to an electrical ground.
20. The method according to claim 19 , wherein the first voltage potential is applied to the first region to perform a write logic low operation.
21. The method according to claim 20 , wherein at least one third voltage potential applied to the body region is a negative voltage potential to repel majority charge carriers from the body region in order to perform the write logic low operation.
22. The method according to claim 19 , wherein the second voltage potential applied to the second region and at least one of the third voltage potentials applied to the body region are to perform a write logic low operation.
23. The method according to claim 22 , wherein the at least one of the third voltage potentials applied to the body region is a negative voltage potential that tunnels minority charge carriers into the body region in order to perform the write logic low operation.
24. The method according to claim 19 , wherein the second voltage potential applied to the second region and at least one of the third voltage potentials applied to the body region are positive voltage potentials in order to perform a write logic high operation.
25. The method according to claim 24 , wherein the positive voltage potentials applied to the second region and the body region creates a band-to-band tunneling effect to tunnel majority charge carriers to the body region in order to perform the write logic high operation.
26. The method according to claim 19 , wherein the second voltage potential applied to the second region and at least one of the third voltage potentials applied to the body region are to perform a write logic high operation.
27. The method according to claim 26 , wherein majority charge carriers are injected into the body region to perform the write logic high operation.
28. The method according to claim 19 , wherein the second voltage potential applied to the second region and at least one of the third voltage potentials applied to the body region are positive voltage potentials in order to perform a read operation.