3D semiconductor device and structure
A 3D integrated circuit device, including: a first layer including first transistors, overlaid by a second layer including second transistors, overlaid by a third layer including third transistors, where the first layer, the second layer and the third layer are each thinner than 2 microns, where the first layer includes first circuits including at least one of the first transistors, where the second layer includes second circuits including at least one of the second transistors, and where the third layer includes a charge pump circuit and control circuits to control the first circuits and the second circuits.
1. A 3D integrated circuit device, the device comprising:
a first level comprising first transistors, overlaid by a second level comprising second transistors, overlaid by a third level comprising third transistors, said third transistors each comprise a single crystal channel,
wherein said second level is thinner than 0.4 microns,
wherein said first level comprises a first array of first memory cells, each of said first memory cells comprising at least one of said first transistors,
wherein said second level comprises a second array of second memory cells, each of said second memory cells comprising at least one of said second transistors, and
wherein said third level comprises a charge pump circuit and control circuits to control said charge pump circuit; and
a plurality of connections connecting from said third transistors to said second transistors forming a multiplicity of connection paths,
wherein said multiplicity of connection paths comprise copper to copper bonded links.
2. The device according to claim 1 ,
wherein said second transistors are self-aligned to said first transistors, being processed following the same lithography step.
3. The device according to claim 1 , further comprising:
memory control circuits,
wherein said memory control circuits comprise a plurality of said third transistors.
4. The device according to claim 1 ,
wherein at least one of said second transistors comprises SiGe.
5. The device according to claim 1 ,
wherein said third level comprises an Electro Static Discharge (“ESD”) circuit.
6. The device according to claim 1 ,
wherein an area I/O circuit comprises at least one of said third transistors.
7. The device according to claim 1 ,
wherein at least one of said second transistors is a vertical transistor.
8. A 3D integrated circuit device, the device comprising:
a first level comprising first transistors, overlaid by a second level comprising second transistors, overlaid by a third level comprising third transistors,
wherein said second level is thinner than 0.4 microns,
wherein said second level comprises a second array of second memory cells, each of said second memory cells comprising at least one of said second transistors, and
wherein said third level comprises a charge pump circuit and control circuits to control said charge pump circuit, and an electrostatic discharge (“ESD”) structure, and
a plurality of connections connecting from said third transistors to said second transistors forming a multiplicity of connection paths,
wherein said multiplicity of connection paths comprise copper to copper bonded links.
9. The device according to claim 8 ,
wherein said second transistors are self-aligned to said first transistors, being processed following the same lithography step.
10. The device according to claim 8 , further comprising:
memory control circuits,
wherein said memory control circuits comprise a plurality of said third transistors.
11. The device according to claim 8 ,
wherein at least one of said second transistors comprises SiGe.
12. The device according to claim 8 ,
wherein at least one of said second transistors is a vertical transistor.
13. The device according to claim 8 ,
wherein an area I/O circuit comprises at least one of said third transistors.
14. A 3D integrated circuit device, the device comprising:
a first level comprising first transistors, overlaid by a second level comprising second transistors, overlaid by a third level comprising third transistors,
wherein said second level is thinner than 0.4 microns,
wherein said first level comprises a first array of first memory cells, each of said first memory cells comprising at least one of said first transistors,
wherein said second level comprises a second array of second memory cells, each of said second memory cells comprising at least one of said second transistors, and
wherein said third level comprises a charge pump circuit and control circuits to control said charge pump circuit; and
a plurality of connections connecting from said third transistors to said second transistors forming a multiplicity of connection paths,
wherein said multiplicity of connection paths comprise copper to copper bonded links.
15. The device according to claim 14 ,
wherein said second transistors are self-aligned to said first transistors.
16. The device according to claim 14 , further comprising:
a memory periphery circuit comprising at least one of said third transistors,
wherein said memory periphery circuit is controlling at least one of said first memory cells and at least one of said second memory cells.
17. The device according to claim 14 ,
wherein at least one of said second transistors comprises SiGe.
18. The device according to claim 14 ,
wherein said third level comprises an Electro Static Discharge (“ESD”) circuit.
19. The device according to claim 14 ,
wherein an area I/O circuit comprises at least one of said third transistors.
20. The device according to claim 14 ,
wherein at least one of said second transistors is a vertical transistor.