Semiconductor device having a SiGe epitaxial layer containing Ga
A semiconductor device includes a field effect transistor (FET). The FET includes a channel region and a source/drain region disposed adjacent to the channel region. The FET also includes a gate electrode disposed over the channel region. The FET is an n-type FET and the channel region is made of Si. The source/drain region includes an epitaxial layer including Si 1−x−y M1 x M2 y , where M1 is one or more of Ge and Sn, and M2 is one or more of P and As, and 0.01≤x≤0.1.
1. A semiconductor device including a field effect transistor (FET), the FET comprising:
a fin structure having an upper portion protruding from an isolation insulating layer, the upper portion of the fin structure including a channel region and a source/drain region disposed adjacent to the channel region;
a gate electrode disposed over the channel region;
a source/drain epitaxial layer disposed over the source/drain region; and
a source/drain contact contacting the source/drain epitaxial layer and the isolation insulating layer, wherein:
a part of the source/drain contact is disposed between the isolation insulating layer and a dielectric layer disposed between the fin structure and an adjacent fin structure,
the channel region and the source/drain region of the fin structure are made of Si,
the source/drain epitaxial layer includes Ge containing Ga, and
a concentration of Ga is in a range from 1×10 18 atoms/cm 3 to 1×10 22 atoms/cm 3 .
2. The semiconductor device of claim 1 , wherein the FET is a p-type FET.
3. The semiconductor device of claim 1 , wherein the concentration of Ga is in a range from 1×10 21 atoms/cm 3 to 1×10 22 atoms/cm 3 .
4. The semiconductor device of claim 2 , wherein the epitaxial layer is further doped with boron or indium.
5. The semiconductor device of claim 2 , wherein a concentration of Ga decreases from an outer surface of the epitaxial layer toward inside the epitaxial layer.
6. A semiconductor device including fin field effect transistors (FinFETs), comprising:
a p-type FinFET including a first fin structure having a channel region made of Si, a first source/drain structure and a first source/drain contact in contact with the first source/drain structure; and
an n-type FinFET including a second fin structure having a channel region made of Si, a second source/drain structure and a second source/drain contact in contact with the second source/drain structure, wherein:
the first source/drain structure includes a first epitaxial layer made of Si 1-x Ge x doped with Ga, where 0.6≤x<1.0,
the semiconductor device further comprises:
an isolation insulating layer in which bottom portions of the first and second fin structures are embedded; and
an dielectric layer disposed on the isolation insulating layer and between the p-type FinFET and the n-type FinFET,
the dielectric layer has a body layer and a first layer between the body layer and the first source/drain contact and the first layer and a second layer between the body layer and the isolation insulating layer, no second layer being disposed between the body layer and the first source/drain contact.
7. The semiconductor device of claim 6 , wherein a concentration of Ga increases from a region adjacent to the first fin structure to a region adjacent to an outer surface of the first epitaxial layer.
8. The semiconductor device of claim 7 , wherein the concentration of Ga continuously increases.
9. A semiconductor device including a field effect transistor (FET), the FET comprising:
a fin structure having an upper portion protruding from an isolation insulating layer, the upper portion of the fin structure including a channel region and a source/drain region disposed adjacent to the channel region;
a gate electrode disposed over the channel region; and
a source/drain contact, wherein:
the FET is a p-type FET,
the channel region and the source/drain region are made of Si,
an epitaxial layer is formed over the source/drain region of the fin structure, the epitaxial layer including SiGeSn doped with Ga, where an amount of Ge is 60 atomic % or more, and wrapping around a top and side faces of the source/drain region of the fin structure,
the epitaxial layer wraps around only one fin structure, and has a hexagonal shape, of which two side are vertical and parallel to the source/drain region in a cross section,
the source/drain contact wraps around the epitaxial layer and is in contact with the isolation insulating layer, and
a part of the source/drain contact is disposed between the isolation insulating layer and a dielectric layer disposed between the fin structure and an adjacent fin structure.
10. The semiconductor device of claim 9 , wherein a concentration of Ga in the source/drain epitaxial layer is not uniform.
11. The semiconductor device of claim 9 , wherein a concentration of Ga is in a range from 1×10 19 atoms/cm 3 to 1×10 21 atoms/cm 3 .
12. The semiconductor device of claim 1 , wherein a lateral thickness of the epitaxial layer on side faces of the fin structure is in a range from 2 nm to 10 nm.
13. The semiconductor device of claim 6 , wherein a conductive layer penetrates under the dielectric layer and is in direct contact with the layer of the second dielectric material and the layer of the third dielectric material.
14. The semiconductor device of claim 13 , wherein the conductive layer includes one of W, Ti, Ni, Co and Ta.
15. The semiconductor device of claim 6 , wherein a part of the first source/drain contact is disposed between the isolation insulating layer and the dielectric layer.
16. The semiconductor device of claim 6 , wherein the concentration of Ga is in a range from 1×10 21 atoms/cm 3 to 1×10 22 atoms/cm 3 .
17. The semiconductor device of claim 1 , wherein the epitaxial layer further includes Sn.
18. The semiconductor device of claim 1 , wherein the dielectric layer includes three layers and the source/drain contact contacts two of the three layers.