Semiconductor integrated circuit device having a first cell row and a second cell row
Disclosed herein is a semiconductor integrated circuit device which includes a standard cell with a plurality of fins extending in a first direction and arranged in a second direction that is perpendicular to the first direction. An active fin of the fins forms part of an active transistor. A dummy fin of the fins is disposed between the active fin and an end of the standard cell.
1. A semiconductor integrated circuit device comprising:
a first cell row comprising standard cells arranged in a first direction; and
a second cell row comprising standard cells arranged in the first direction, and disposed adjacent to the first cell row in a second direction perpendicular to the first direction, wherein:
the first cell row comprises:
a first standard cell having an active transistor with a fin structure, the active transistor having a first fin extending in the first direction and a first gate line extending in the second direction; and
a second standard cell which is a TAP cell, the second standard cell being adjacent to the first standard cell in the first direction, and including a first dummy fin extending in the first direction and a diffusion region supplied with power; and
a third standard cell having a second fin extending in the first direction, and
the first fin is disposed closest to a cell row boundary between the first and second cell rows, the first dummy fin and the second fin are disposed at the same position in the second direction as the first fin, and the diffusion region is disposed farther away from the cell row boundary than the first dummy fin in the second direction.
2. The semiconductor integrated circuit device of claim 1 , wherein the second fin is an active fin.
3. The semiconductor integrated circuit device of claim 2 , the third standard cell further having a second dummy fin extending in the first direction and being disposed at the same position in the second direction as the first fin.
4. The semiconductor integrated circuit device of claim 1 , wherein the second fin is a dummy fin.
5. A semiconductor integrated circuit device comprising:
a first cell row comprising standard cells arranged in a first direction; and
a second cell row comprising standard cells arranged in the first direction, and disposed adjacent to the first cell row in a second direction perpendicular to the first direction, wherein:
the first cell row comprises:
a first standard cell comprising an active transistor with a fin structure, the active transistor having a first fin extending in the first direction and a first gate line extending in the second direction; and
a second standard cell which is a TAP cell, the second standard cell being adjacent to the first standard cell in the first direction, and including a first dummy fin extending in the first direction and a diffusion region supplied with power; and
the first fin is disposed closest to a cell row boundary between the first and second cell rows, the first dummy fin is disposed at the same position in the second direction as the first fin, and the diffusion region is disposed farther away from the cell row boundary than the first dummy fin in the second direction, and
the second cell row comprises:
a third standard cell comprising a second fin, the second fin is disposed closest to the cell row boundary.
6. The semiconductor integrated circuit device of claim 5 , the second cell row further comprising a fourth standard cell comprising a third fin, the third fin is disposed at the same position in the second direction as the second fin.
7. The semiconductor integrated circuit device of claim 5 ,
the first cell row further comprising a fifth standard cell having a fourth fin extending in the first direction, and
the fourth fin is disposed at the same position in the second direction as the first fin.
8. The semiconductor integrated circuit device of claim 7 , wherein the fourth fin is an active fin.
9. The semiconductor integrated circuit device of claim 8 , the fifth standard cell further having a second dummy fin extending in the first direction and being disposed at the same position in the second direction as the first fin.
10. The semiconductor integrated circuit device of claim 7 , wherein the fourth fin is a dummy fin.