Semiconductor structures employing strained material layers with defined impurity gradients and methods for fabricating same
Semiconductor structures and devices including strained material layers having impurity-free zones, and methods for fabricating same. Certain regions of the strained material layers are kept free of impurities that can interdiffuse from adjacent portions of the semiconductor. When impurities are present in certain regions of the strained material layers, there is degradation in device performance. By employing semiconductor structures and devices (e.g., field effect transistors or “FETs”) that have the features described, or are fabricated in accordance with the steps described, device operation is enhanced.
1. A method of forming a semiconductor device, the method comprising:
forming an isolation well in a substrate;
depositing a strained semiconductor layer on a surface of the isolation well;
depositing a gate dielectric over the strained semiconductor layer;
depositing a gate electrode over the gate dielectric; and
doping the semiconductor device with a first concentration of an impurity in a first portion adjacent to an interface between the strained semiconductor layer and the substrate, a second concentration of the impurity in a second portion distal from the interface, and a third concentration in a third portion disposed between the first portion and the second portion, the first concentration being greater than the second concentration, the third concentration being greater than the second concentration.
2. The method of claim 1 further comprising depositing and etching a dielectric layer to form gate spacers on opposing sidewalls of the gate dielectric and gate electrode, wherein the opposing sidewalls of the gate dielectric extend in a direction perpendicular to a major surface of the substrate.
3. The method of claim 1 , wherein providing a substrate comprises providing a multi-layer substrate.
4. The method of claim 1 , wherein depositing the strained semiconductor layer comprises depositing a plurality of overlayers.
5. The method of claim 4 , wherein depositing the plurality of overlayers comprises depositing a plurality of Si 3 N 4 overlayers.
6. The method of claim 1 , wherein depositing the strained semiconductor layer further comprises creating underlying voids in the strained semiconductor layer.
7. The method of claim 6 , wherein creating the underlying voids in the strained semiconductor layer comprises implantation of one or more gases followed by annealing.
8. The method of claim 1 , wherein the second concentration is set to zero within the isolation well.
9. The method of claim 1 , wherein depositing a strained semiconductor layer comprises depositing a multi-layer strained semiconductor layer.
10. The method of claim 1 , wherein depositing the strained semiconductor layer comprises depositing a Si, Ge, or SiGe strained semiconductor layer.
11. A method of forming a semiconductor structure comprising:
forming a substrate having multiple layers;
forming one or more strained layers over the substrate; and
providing an impurity gradient along an axis orthogonal to a top surface of the one or more strained layers and a bottom surface of the substrate, the impurity gradient having a value equal to zero at the bottom surface of the substrate, having a value equal to zero at a distal zone of the one or more strained layers, and having a peak within one of the substrate multiple layers.
12. The method of claim 11 further comprising inducing a strain in the one or more strained layers by lattice mismatch.
13. The method of claim 11 further comprising mechanically inducing a strain in the one or more strained layers.
14. The method of claim 11 further comprising inducing a strain in the one or more strained layers by depositing overlayers comprising Si 3 N 4 .
15. The method of claim 11 , wherein providing the impurity gradient comprises providing a boron, phosphorous, or arsenic dopant impurity gradient.
16. The method of claim 11 , wherein forming one or more strained layers over the substrate comprises forming one or more strained layers having a distal zone at least fifty Angstroms in thickness.
17. A method comprising:
doping a substrate with an impurity to form a channel region;
forming a strained channel layer on a surface of the substrate over the channel region, the strained channel layer comprises a first concentration of an impurity in a first portion adjacent an interface with the substrate, a second concentration of the impurity in a second portion distal from the interface, and a third concentration in a third portion disposed between the first portion and the second portion, the first concentration being greater than the second concentration, the third concentration being greater than the second concentration; and
forming a gate structure over the strained channel layer.
18. The method of claim 17 , wherein the impurity is an n-type dopant or a p-type dopant.
19. The method of claim 17 , wherein the impurity is silicon or germanium.
20. The method of claim 17 , wherein the substrate comprises a crystalline material that is lattice mismatched to the strained channel layer, the crystalline material adjoining the strained channel layer.