Semiconductor memory device capable of reducing chip size
According to one embodiment, a first well of the first conductivity type which is formed in a substrate. a second well of a second conductivity type which is formed in the first well. The plurality of memory cells, the plurality of first bit line select transistors, and the plurality of second bit line select transistors are formed in the second well, and the plurality of first bit line select transistors and the plurality of second bit line select transistors are arranged on a side of the sense amplifier with respect to the plurality of memory cells of the plurality of bit lines.
1. A semiconductor memory device comprising:
a substrate, a first well of a first conductively type being formed in the substrate, a second well of a second conductively type being formed in the first well;
a sense amplifier;
a plurality of first memory cells of the first conductivity type;
a plurality of bit lines connected to the plurality of first memory cells;
a first source line connected to the plurality of first memory cells;
a plurality of first bit line select transistors of the first conductivity type which selectively connect a first of the plurality of bit lines to the sense amplifier;
a plurality of second bit line select transistors of the first conductivity type which selectively connect a second of the plurality of bit lines to the first source line;
a plurality of second memory cells of the first conductivity type; and
a second source line connected to the plurality of second memory cells,
wherein
the plurality of first memory cells, the plurality of first bit line select transistors, and the plurality of second bit line select transistors are formed in the second well, and
the plurality of second bit line select transistors are further connected to the second source line.
2. The device according to claim 1 , wherein
the plurality of second bit line select transistors apply a potential of the first source line to the second of the plurality of bit lines in an erase mode.
3. The device according to claim 1 , wherein
the plurality of second memory cells are formed in the second well.
4. The device according to claim 1 , wherein
the plurality of first bit line select transistors are arranged between the plurality of first memory cells and the sense amplifier, and
the plurality of second bit line select transistors are arranged between the first source line and the second source line.
5. The device according to claim 1 , wherein
an erase voltage is applied to the second well in an erase mode.
6. The device according to claim 5 , wherein
the plurality of bit lines and the first source line are set in a floating state in the erase mode.
7. The device according to claim 1 , wherein
a source line voltage is applied to the another one of the plurality of bit lines.
8. The device according to claim 1 , wherein
the plurality of first memory cells form NAND strings.