Semiconductor package
A semiconductor package includes a semiconductor chip; a connection member having a first surface on which the semiconductor chip is disposed and a second surface opposing the first surface, an encapsulant disposed on the first surface of the connection member and encapsulating the semiconductor chip, a passivation layer on the second surface of the connection member; and an UBM layer partially embedded in the passivation layer, wherein the UBM layer includes an UBM via embedded in the passivation layer and connected to the redistribution layer of the connection member and an UBM pad connected to the UBM via and protruding from a surface of the passivation layer, and a width of a portion of the UBM via in contact with the UBM pad is narrower than a width of a portion of the UBM via in contact with the redistribution layer.
1. A semiconductor package comprising:
a semiconductor chip having connection pads;
a connection member having a first surface on which the semiconductor chip is disposed and a second surface opposing the first surface, the connection member including a redistribution layer electrically connected to the connection pads;
an encapsulant disposed on the first surface of the connection member and encapsulating the semiconductor chip;
a passivation layer, which is an outermost insulating layer of the semiconductor package, disposed on the second surface of the connection member; and
an underbump metallurgy (UBM) layer partially embedded in the passivation layer and connected to the redistribution layer of the connection member,
wherein the UBM layer includes a UBM via embedded in the passivation layer and connected to the redistribution layer of the connection member and a UBM pad connected to the UBM via and protruding from a surface of the passivation layer,
the UBM pad is partially embedded in the passivation layer such that a portion of the UBM pad is exposed from the passivation layer, and
a width of a portion of the UBM via in contact with the UBM pad is narrower than a width of a portion of the UBM via in contact with the redistribution layer.
2. The semiconductor package of claim 1 , wherein adhesive strength between the UBM via and the redistribution layer is greater than that between the UBM via and the UBM pad.
3. The semiconductor package of claim 1 , wherein the UBM via has a structure integrated with the redistribution layer adjacent to the UBM via.
4. The semiconductor package of claim 1 , wherein a cross-section of the UBM via, when viewed in a thickness direction of the connection member, has a trapezoidal shape.
5. The semiconductor package of claim 1 , wherein a surface of the UBM pad exposed from the passivation layer has a recess.
6. The semiconductor package of claim 1 , wherein a surface of the UMB pad exposed from the passivation layer has a plurality of recesses separated from each other.
7. The semiconductor package of claim 1 , wherein an upper surface of the semiconductor chip, opposing a surface of the semiconductor chip on which the connection pads are disposed, and an upper surface of the encapsulant are substantially coplanar with each other.
8. The semiconductor package of claim 1 , wherein the UBM via includes a plurality of UBM vias connected to the respective UBM pads.
9. The semiconductor package of claim 1 , further comprising a connection terminal disposed on the UBM pad.
10. The semiconductor package of claim 9 , wherein the connection terminal comprises a solder ball.
11. A semiconductor package comprising:
a connection member having first and second surfaces opposing each other and including an insulating layer and a first redistribution layer at least partially embedded in the insulating layer;
a semiconductor chip disposed on the first surface of the connection member and having connection pads electrically connected to the first redistribution layer;
an encapsulant disposed on the first surface of the connection member and encapsulating the semiconductor chip;
an underbump metallurgy (UBM) via disposed on the second surface of the connection member and connected to the first redistribution layer of the connection member;
a passivation layer, which is an outermost insulating layer of the semiconductor package, disposed on the second surface of the connection member and embedding the UBM via therein, the passivation layer including an insulating material different from that of the insulating layer; and
a UBM pad connected to the UBM via and protruding from a surface of the passivation layer,
wherein the UBM via has a structure integrated with a portion of the first redistribution layer in contact with the UBM via, and
wherein the UBM pad is partially embedded in the passivation layer such that a portion of the UBM pad is exposed from the passivation layer.
12. The semiconductor package of claim 11 , wherein the connection member further includes a second redistribution layer disposed on the insulating layer, and a connection via in the insulating layer and connecting the first and second redistribution layers to each other.
13. The semiconductor package of claim 12 , wherein a width of a first portion of the connection via in contact with the second redistribution layer is greater than a width of a second portion of the connection via in contact with the first redistribution layer.
14. The semiconductor package of claim 12 , wherein a width of a portion of the UBM via in contact with the UBM pad is narrower than a width of a portion of the UBM via in contact with the first redistribution layer.
15. The semiconductor package of claim 11 , further comprising a connection terminal disposed on the UBM pad.
16. The semiconductor package of claim 15 , wherein the connection terminal comprises a solder ball.
17. A connection member comprising:
an insulating layer having a first surface and a second surface opposing the first surface;
a redistribution layer disposed in the insulating layer;
a passivation layer, which is an outermost insulating layer of the connection member, disposed on the second surface; and
an underbump metallurgy (UBM) layer partially embedded in the passivation layer, the UBM layer being connected to the redistribution layer,
wherein a portion of the redistribution layer is exposed from the first surface and is connected to connection pads of a semiconductor chip,
the UBM layer comprises a UBM via embedded in the passivation layer and connected to the redistribution layer, and a UBM pad connected to the UBM via and protruding from a surface of the passivation layer,
the UBM pad is partially embedded in the passivation layer such that a portion of the UBM pad is exposed from the passivation layer, and
a width of a portion of the UBM via in contact with the UBM pad is narrower than a width of a portion of the UBM via in contact with the redistribution layer.
18. The connection member of claim 17 , wherein the UBM via has a structure integrated with a portion of the redistribution layer in contact with the UBM via.
19. The connection member of claim 17 , wherein the UBM via includes a plurality of UBM vias connected to the respective UBM pads.
20. The connection member of claim 17 , wherein the redistribution layer comprises a plurality of redistribution layers disposed on different levels in the insulating layer, and the connection member further comprises at least one via electrically connecting the plurality of redistribution layers to each other.
21. The connection member of claim 17 , further comprising a connection terminal disposed on the UBM pad.
22. The connection member of claim 21 , where the connection terminal comprises a solder ball.