Semiconductor package
A semiconductor package is provided. The semiconductor package includes a redistribution structure having a front surface and a rear surface opposite the front surface, the redistribution structure including an insulating layer and a redistribution conductor provided in the insulating layer; a semiconductor chip provided on the rear surface and including a connection pad electrically connected to the redistribution conductor; an encapsulant provided on at least a portion of the semiconductor chip; under-bump metal (UBM) vias extending from the redistribution conductor to the front surface of the redistribution structure within the insulating layer; UBM pads provided on the front surface of the redistribution structure to correspond to the UBM vias, respectively, and each UBM pad of the UBM pads having an exposed surface convexly protruding away from the front surface of the redistribution structure; and a metal bump provided on the UBM pads and contacting the exposed surface of each UBM pad of the UBM pads.
1 . A semiconductor package comprising:
a redistribution structure having a front surface and a rear surface opposite the front surface, the redistribution structure comprising an insulating layer and a redistribution conductor provided in the insulating layer;
a semiconductor chip provided on the rear surface and comprising a connection pad electrically connected to the redistribution conductor;
an encapsulant provided on at least a portion of the semiconductor chip;
under-bump metal (UBM) vias extending from the redistribution conductor to the front surface of the redistribution structure within the insulating layer;
UBM pads provided on the front surface of the redistribution structure to correspond to the UBM vias, respectively, and each UBM pad of the UBM pads having an exposed surface convexly protruding away from the front surface of the redistribution structure; and
a metal bump provided on the UBM pads and contacting the exposed surface of each UBM pad of the UBM pads,
wherein a boundary surface of the metal bump and each of the UBM pads is defined by the exposed surface of each of the UBM pads, and the metal bump extends between the exposed surface of at least two UBM pads, of the UBM pads, that are provided within a perimeter of the metal bump.
2 . The semiconductor package of claim 1 , wherein each UBM pad of the UBM pads has a central portion overlapping the UBM vias along a first direction perpendicular to the front surface of the redistribution structure, and an edge portion which does not overlap the UBM vias along the first direction, and
wherein a thickness of the central portion is greater than a thickness of the edge portion.
3 . The semiconductor package of claim 2 , wherein the edge portion extends, in a second direction parallel to the front surface of the redistribution structure, at least 0.5 μm past the central portion.
4 . The semiconductor package of claim 2 , wherein a maximum thickness of the central portion along the first direction is about 20 μm or less.
5 . The semiconductor package of claim 1 , wherein a diameter of a circumference of the metal bump contacting the exposed surface is about 150 μm or more.
6 . The semiconductor package of claim 1 , wherein each UBM via of the UBM vias has a diameter of about 20 μm or more.
7 . The semiconductor package of claim 1 , wherein the UBM pads and the UBM vias overlap the metal bump along a first direction perpendicular to the front surface of the redistribution structure.
8 . The semiconductor package of claim 1 , wherein the UBM pads are spaced apart from each other, and
wherein the metal bump is in direct contact with the insulating layer between the at least two UBM pads that are provided within the perimeter of the metal bump.
9 . The semiconductor package of claim 1 , wherein the redistribution structure comprises a fan-in region overlapping the semiconductor chip along a first direction perpendicular to the rear surface, and a fan-out region extending from the fan-in region in a second direction parallel to the rear surface.
10 . A semiconductor package comprising:
a redistribution structure having a front surface and a rear surface opposite the front surface, the redistribution structure comprising a redistribution conductor and an insulating layer provided on the redistribution conductor, the insulating layer defining a first via hole exposing a first portion of the redistribution conductor and a second via hole exposing a second portion of the redistribution conductor;
a semiconductor chip provided on the rear surface and comprising a connection pad electrically connected to the redistribution conductor;
a first under-bump metal (UBM) structure electrically connected to the redistribution conductor exposed through the first via hole and a second UBM structure electrically connected to the redistribution conductor exposed through the second via hole; and
a metal bump provided on the first UBM structure and the second UBM structure,
wherein the first UBM structure comprises:
a first seed layer extending along an inner surface of the first via hole;
a first UBM via provided on the first seed layer in the first via hole; and
a first UBM pad having a first surface and a second surface, the first surface of
the first UBM structure extending in a direction parallel to the front surface of the redistribution structure and contacting the first UBM via, and the second surface convexly protruding away from the first surface of the first UBM structure and contacting the metal bump,
wherein a second UBM pad of the second UBM structure comprises a first surface and a second surface, the second surface of the second UBM structure convexly protruding away from the first surface of the second UBM structure and contacting the metal bump, and
wherein a boundary surface of the metal bump and the first UBM pad is defined by the second surface of the first UBM pad, a boundary surface of the metal bump and the second UBM pad is defined by the second surface of the second UBM pad, and the metal bump extends between the second surface of the first UBM pad and the second surface of the second UBM pad, within a perimeter of the metal bump.
11 . The semiconductor package of claim 10 , wherein the inner surface of the first via hole comprises an inner side surface of the insulating layer and a surface of the redistribution conductor exposed through the first via hole, and
wherein the first seed layer conformally extends along the inner side surface of the insulating layer, the surface of the redistribution conductor, and a portion of the front surface of the redistribution structure.
12 . The semiconductor package of claim 11 , wherein the first surface of the first UBM pad contacts the first seed layer along the portion of the front surface of the redistribution structure.
13 . The semiconductor package of claim 10 , wherein the second surface of the first UBM pad and the second surface of the second UBM pad are completely covered by the metal bump.
14 . The semiconductor package of claim 10 , wherein the first UBM via and the first UBM pad comprise copper (Cu) or a copper (Cu) alloy, and
wherein the first seed layer comprises titanium (Ti) or a titanium (Ti) alloy.
15 . The semiconductor package of claim 10 , wherein the metal bump comprises tin (Sn) or a tin (Sn) alloy.
16 . A semiconductor package comprising:
a redistribution structure having a front surface and a rear surface opposite the front surface, the redistribution structure comprising a redistribution conductor, and an insulating layer provided on the redistribution conductor, the insulating layer defining a first via hole exposing a first portion of the redistribution conductor and a second via hole exposing a second portion of the redistribution conductor;
a semiconductor chip provided on the rear surface and comprising a connection pad electrically connected to the redistribution conductor;
a first under-bump metal (UBM) structure electrically connected to the redistribution conductor exposed through the first via hole and a second UBM structure electrically connected to the redistribution conductor exposed through the second via hole; and
a metal bump provided on the first UBM structure and the second UBM structure,
wherein the first UBM structure comprises:
a first seed layer extending along an inner surface of the first via hole and a portion of the front surface of the redistribution structure,
a first UBM via provided on the first seed layer in the first via hole, and
a first UBM pad extending in a first direction parallel to the front surface of the redistribution structure, the first UBM pad having a first surface contacting the first UBM via and a portion of the first seed layer, and a second surface convexly protruding away from the first and surface of the first UBM pad,
wherein a second UBM pad of the second UBM structure comprises a first surface and a second surface, the second surface of the second UBM structure convexly protruding away from the first surface of the second UBM structure, and
wherein a boundary surface of the metal bump and the first UBM pad is defined by the second surface of the first UBM pad, a boundary surface of the metal bump and the second UBM pad is defined by the second surface of the second UBM pad, and the metal bump extends between the second surface of the first UBM pad and the second surface of the second UBM pad, within a perimeter of the metal bump.
17 . The semiconductor package of claim 16 , wherein the first UBM pad has a central portion overlapping the first UBM via along a second direction perpendicular to the front surface of the redistribution structure, and an edge portion provided around a perimeter of the central portion, and
wherein a first portion of the second surface corresponding to the central portion is farther from the first surface than a second portion of the second surface corresponding to the edge portion.