Configurable computing array die based on printed memory and two-sided integration
View Patent ↗The present invention discloses a new type of configurable gate array—a configurable computing array die based on two-sided integration. It is a monolithic die and comprises at least a configurable computing element and a configurable logic element formed on different sides of a semiconductor substrate. Each configurable computing element can selectively realize a basic function from a math library. It comprises a plurality of printed arrays for storing the look-up tables (LUT) for different basic functions.
1. A configurable computing array die, comprising:
a semiconductor substrate having a first side and a second side;
at least a configurable computing element formed on said first side, said configurable computing element comprising:
a first printed array for storing a first look-up table (LUT) of a first basic function;
a second printed array for storing a second LUT of a second basic function;
a plurality of internal configurable interconnects coupling said first and second printed arrays;
wherein said configurable computing element selectively realizes said first or second basic function by programming said internal configurable interconnects;
at least a configurable logic element formed on said second side of said semiconductor substrate, wherein said configurable logic element selectively realizes a logic function from a logic library;
a plurality of through-substrate vias through said semiconductor substrate for coupling said configurable computing element and said configurable logic element;
wherein said configurable computing array die realizes a complex math function by programming said configurable computing element and said configurable logic element.
2. The configurable computing array die according to claim 1 , wherein said first and second printed arrays are placed side-by-side.
3. The configurable computing array die according to claim 1 , wherein said second printed array is stacked above said first printed array.
4. The configurable computing array die according to claim 3 , wherein said second printed array at least partially covers said first printed array.
5. The configurable computing array die according to claim 1 , wherein said first and second LUTs are respectively recorded into said first and second printed arrays using a printing method during manufacturing.
6. The configurable computing array die according to claim 5 , wherein said printing method is photo-lithography, nano-imprint, e-beam lithography, DUV lithography, or laser-programming.
7. The configurable computing array die according to claim 1 , wherein said first side is a front side and said second side is a back side.
8. The configurable computing array die according to claim 1 , wherein said first side is a back side and said second side is a front side.
9. A configurable computing array die, comprising:
a semiconductor substrate having a first side and a second side;
at least a configurable computing element formed on said first side, said configurable computing element comprising:
a first printed array for storing a first look-up table (LUT) of a first basic function;
a second printed array for storing a second LUT of a second basic function;
a plurality of internal configurable interconnects coupling said first and second printed arrays;
wherein said configurable computing element selectively realizes said first or second basic function by programming said internal configurable interconnects;
at least a configurable logic element formed on said second side of said semiconductor substrate, wherein said configurable logic element selectively realizes a logic function from a logic library;
a plurality of through-substrate vias through said semiconductor substrate for coupling said configurable computing element and said configurable logic element;
at least a configurable interconnect for selectively realizing an interconnect from an interconnect library;
wherein said configurable computing array die realizes a complex math function by programming said configurable computing element, said configurable logic element and said configurable interconnect.
10. The configurable computing array die according to claim 9 , wherein said first and second printed arrays are placed side-by-side.
11. The configurable computing array die according to claim 9 , wherein said second printed array is stacked above said first printed array.
12. The configurable computing array die according to claim 11 , wherein said second printed array at least partially covers said first printed array.
13. The configurable computing array die according to claim 9 , wherein said first printed array is stacked above said internal configurable interconnects.
14. The configurable computing array die according to claim 9 , wherein said second printed array is stacked above said internal configurable interconnects.
15. The configurable computing array die according to claim 9 , wherein said configurable interconnect is formed on said first side.
16. The configurable computing array die according to claim 9 , wherein said configurable interconnect is formed on said second side.
17. The configurable computing array die according to claim 9 , wherein said first and second LUTs are respectively recorded into said first and second printed arrays using a printing method during manufacturing.
18. The configurable computing array die according to claim 17 , wherein said printing method is photo-lithography, nano-imprint, e-beam lithography, DUV lithography, or laser-programming.
19. The configurable computing array die according to claim 9 , wherein said first side is a front side and said second side is a back side.
20. The configurable computing array die according to claim 9 , wherein said first side is a back side and said second side is a front side.