Semiconductor memory device and method of manufacturing the same

1. A semiconductor memory device comprising:

a separation member defining active regions of a substrate; and

gate lines intersecting the active regions and each buried in a trench formed in the substrate,

wherein each of the gate lines comprises: a lower electrode structure; and an upper electrode structure on the lower electrode structure,

wherein the upper electrode structure comprises:

a source layer substantially covering a sidewall of the trench and including a work-function adjustment element;

a conductive layer on the source layer; and

a work-function adjustment layer disposed between the source layer and the conductive layer,

wherein the work-function adjustment layer includes a material different from that of the source layer and is doped with the work-function adjustment element.

2. The semiconductor memory device of claim 1 , wherein a work function of the lower electrode structure is higher than a work function of the upper electrode structure.

3. The semiconductor memory device of claim 1 , wherein the source layer and the conductive layer are spaced apart from each other by the work-function adjustment layer.

4. The semiconductor memory device of claim 3 , wherein the work-function adjustment layer conformally covers an inner sidewall of the source layer.

5. The semiconductor memory device of claim 1 , further comprising:

a gate insulating pattern on the sidewall of the trench, wherein the gate insulating pattern separates the gate line from the substrate, and

wherein a portion of the gate insulating pattern adjacent to the upper electrode structure laterally protrudes toward the conductive layer.

6. The semiconductor memory device of claim 1 , wherein the source layer extends between the lower electrode structure and the conductive layer to cover a top surface of the lower electrode structure.

7. The semiconductor memory device of claim 6 , wherein the source layer and the lower electrode structure have a gap provided therebetween, and

wherein the gap is substantially filled with oxygen or nitrogen.

8. The semiconductor memory device of claim 1 , wherein the work-function adjustment layer includes a metal or a metal nitride, and

wherein the work-function adjustment element includes lanthanum (La).

9. The semiconductor memory device of claim 1 , further comprising:

a diffusion layer disposed between the work-function adjustment layer and the conductive layer,

wherein the diffusion layer includes a same material as the work-function adjustment layer.

10. The semiconductor memory device of claim 1 , further comprising:

dopant injection regions disposed in the active regions, the dopant injection regions comprising: first dopant injections regions disposed in the active regions between the gate lines; and second dopant injection regions disposed in the active regions between the separation member and the gate lines;

bit lines provided on the substrate and connected to the first dopant injection regions; and

capacitors provided on the substrate and connected to the second dopant injection regions.

11. A semiconductor memory device comprising:

a substrate comprising a separation member defining active regions arranged in a first direction;

gate lines each buried in a trench formed in an upper portion of the substrate, the gate lines intersecting the active regions in a second direction intersecting the first direction to divide the active regions into first dopant injection regions and second dopant injection regions; and

a bit line disposed on the gate lines and extending in a third direction intersecting both the first and second directions to intersect the gate lines,

wherein each of the gate lines comprises:

a first diffusion layer and a second diffusion layer formed along a bottom surface and a sidewall of the trench;

a work-function adjustment layer disposed between the first diffusion layer and the second diffusion layer; and

a conductive layer on the second diffusion layer,

wherein the first diffusion layer, the second diffusion layer and the work-function adjustment layer include a metal nitride, and

wherein the work-function adjustment layer is doped with a work-function adjustment element different from a metal element of the metal nitride.

12. The semiconductor memory device of claim 11 , wherein a work function of the work-function adjustment layer is lower than a work function of the first diffusion layer and a work function of the second diffusion layer.

13. The semiconductor memory device of claim 11 , further comprising:

a source layer disposed between at least one of the first diffusion layer and the work-function adjustment layer or between the second diffusion layer and the work-function adjustment layer.

14. The semiconductor memory device of claim 13 , wherein the source layer includes the work-function adjustment element of the work-function adjustment layer.

15. A semiconductor memory device comprising:

a substrate comprising a plurality of active regions;

gate lines positioned in the active regions, wherein each of the gate lines is disposed in a trench formed in the substrate,

wherein each of the gate lines comprises: a lower electrode structure; and an upper electrode structure disposed on the lower electrode structure,

wherein the upper electrode structure comprises:

a source layer substantially covering a sidewall of the trench and including a work-function adjustment element;

a conductive layer on the source layer; and

a work-function adjustment layer disposed between the source layer and the conductive layer,

wherein the work-function adjustment layer includes a material different from that of the source layer and is doped with the work-function adjustment element; and

a gap formed between the lower electrode structure and the upper electrode structure.

16. The semiconductor memory device of claim 15 , wherein the gap is substantially filled with nitrogen or oxygen.