Three-dimensional resistive random access memory device containing selectively grown amorphous silicon-containing barrier and method of making the same

1. A method of forming a resistive memory device, comprising:

forming an alternating stack of insulating layers and electrically conductive layers that extend along a first horizontal direction over a substrate, wherein the insulating layers comprise a silicon oxide material;

selectively silylating sidewalls of the insulating layers with a chemical including at least one silyl group without silylating sidewalls of the electrically conductive layers;

forming silicon-containing barrier material portions at least by selectively growing a first silicon-containing barrier material from surfaces of the electrically conductive layers without growing the first silicon-containing barrier material from silylated surfaces of the insulating layers;

forming a memory material layer on the silicon-containing barrier material portions and the sidewalls of the insulating layers; and

forming a vertical conductive line on the memory material layer.

2. The method of claim 1 , wherein sidewalls of the electrically conductive layers comprise metallic nitride surfaces having —ON groups that prevent silylation of the metallic nitride material upon exposure to the chemical.

3. The method of claim 1 , wherein:

the chemical is selected from trimethylsilyl trifluoromethanesulfonate, trimethylsilyl cyanide, trimethylsilyl polyphosphate, tris(trimethylsilyl) phosphite, bis(trimethylsilyl)carbodiimide, trimethylsilyl isocyanate, (trimethylsilyl)phenyl, trifluoromethanesulfonate, and trimethylsilyl acetate; and

molecules of the chemical comprise a trimethylsilyl group (—Si(CH 3 ) 3 ) that combines with an oxygen atom of the silicon oxide material.

4. The method of claim 1 , further comprising:

providing hydrogen-termination on portions of the first silicon-containing barrier material formed by the first selective silicon-containing material deposition process and providing halogen-termination on the sidewalls of the insulating layers; and

growing a second silicon-containing barrier material from surfaces of the first silicon-containing barrier material while suppressing growth of the second silicon-containing barrier material from the sidewalls of the insulating layers, wherein each of the silicon-containing barrier material portions includes a respective portion of the first silicon-containing barrier material and a respective portion of the second silicon-containing barrier material.

5. The method of claim 4 , further comprising:

halogenating surfaces of the portions of the first silicon-containing barrier material and the sidewalls of the insulating layers by treatment with a halogen-containing gas; and

selectively hydrogenating the surfaces of the portions of the first silicon-containing barrier material while the sidewalls of the insulating layers remain halogenated by treatment with a hydrogen-containing gas, to provide the hydrogen-termination on the portions of the first silicon-containing barrier material and the halogen-termination on the sidewalls of the electrically conductive layers.

6. The method of claim 5 , wherein:

the halogen-containing gas is selected from Cl 2 and HBr; and

the hydrogen-containing gas comprises aminosilane (H 2 NSiH 3 ) gas.

7. The method of claim 1 , further comprising:

forming a continuous alternating stack of continuous insulating layers and continuous electrically conductive layers over the substrate; and

patterning the continuous alternating stack into a plurality of staked structures including the alternating stack and additional alternating stacks that are laterally spaced apart among one another by line trenches that extend along the first horizontal direction.

8. The method of claim 7 , further comprising:

forming sacrificial rail structures in the line trenches;

forming pillar cavities by etching through portions of the sacrificial rail structures, whereby each of the sacrificial rail structures is divided into sacrificial pillar structures that are laterally spaced apart along the first horizontal direction by a respective subset of the pillar cavities;

forming dielectric pillar structures in the pillar cavities; and

forming memory openings by removing the sacrificial pillar structures selective to the dielectric pillar structures, wherein the silicon-containing barrier material portions are formed in one of the memory openings.

9. The method of claim 8 , wherein:

the memory material layer is formed within the one of the memory openings and on sidewalls of a neighboring pair of dielectric pillar structures located adjacent to the one of the memory openings;

a first portion of the memory material layer that contacts the alternating stack has a laterally undulating vertical cross-sectional profile; and

second portions of the memory material layer that contact the neighboring pair of dielectric pillar structures and including a respective pair of straight vertical sidewalls.

10. The method of claim 1 , wherein:

the silicon-containing barrier material portions comprise a doped or undoped amorphous silicon;

the electrically conductive layers comprise titanium nitride; and

the memory material layer comprises a continuous oxygen deficient crystalline titanium oxide layer to form a barrier modulated cell (BMC) resistive memory device.