Memory system

1. A memory system accessible from a host, the memory system comprising:

a nonvolatile memory,

a memory controller included in a first package, and

a memory interface circuit included in a second package, the second package being different from the first package, wherein:

the memory controller includes an encoder for performing encoding for error correction, and is configured to:

encode first data into second data using the encoder, and

program the second data into a first location in the nonvolatile memory;

the memory interface circuit is interposed between the nonvolatile memory and the memory controller, includes a decoder for performing decoding for error correction, and is configured to:

read the second data, as third data, from the first location in the nonvolatile memory,

diagnose the third data by decoding the third data using the decoder, and

convey a result of the diagnosis to the memory controller,

the memory controller is further configured to determine, on the basis of the conveyed result of the diagnosis, whether to execute a normal refresh or a reprogramming refresh,

in a case where the normal refresh is to be executed, the memory controller reads the second data, as fourth data, from the first location in the nonvolatile memory, corrects an error bit included in the fourth data by decoding the fourth data to generate fifth data, and programs the fifth data in a second location in the nonvolatile memory, the second location being different from the first location,

in a case where the reprogramming refresh is to be executed, the memory controller issues a reprogramming refresh instruction to the memory interface circuit; and

the memory interface circuit is further configured to:

in response to the reprogramming refresh instruction,

read the second data, as sixth data, from the first location in the nonvolatile memory,

correct an error bit included in the sixth data by decoding the sixth data using the decoder to generate seventh data, and

reprogram, without erasing, the seventh data in the first location in the nonvolatile memory.

2. The memory system according to claim 1 , wherein the memory includes a plurality of memory cells, each of the plurality of memory cells holds a threshold voltage corresponding to a value among a plurality of values,

the memory interface circuit is further configured to:

acquire a margin width on the basis of a number of error bits in the third data, and

convey the acquired margin width to the memory controller as the result of the diagnosis; and

the memory controller is further configured to issue the reprogramming refresh instruction on the basis of a comparison between the margin width and a first threshold value.

3. The memory system according to claim 1 , wherein the memory interface circuit is further configured to:

read data from the first location in the nonvolatile memory twice with different read voltages as two pieces of eighth data,

acquire a number of bits having different values between the two pieces of eighth data, and

convey the acquired number of bits to the memory controller as the result of the diagnosis; and

the memory controller is further configured to issue the reprogramming refresh instruction on the basis of a comparison between a second threshold value and the acquired number of bits.

4. The memory system according to claim 1 , wherein the memory interface circuit is further configured to:

read data from a location in the nonvolatile memory a plurality of times with different read voltages as a plurality of pieces of ninth data,

acquire soft bit information on the basis of the plurality of pieces of the ninth data, and

input the acquired soft bit information to the decoder for execution of error correction.

5. The memory system according to claim 1 , wherein the memory controller is further configured to transmit the second data to the memory interface circuit, and

the memory interface circuit further includes a buffer, and is further configured to:

store, in the buffer, the second data received from the memory controller,

program, in a third location in the nonvolatile memory, the second data,

program tenth data different from the second data in a fourth location, the fourth location being different from the third location in the nonvolatile memory, and

then, reprogram, in the third location, the second data stored in the buffer.

6. The memory system according to claim 1 , wherein the memory controller is further configured to transmit the second data to the memory interface circuit, and

the memory interface circuit further includes a buffer, and is further configured to:

store, in the buffer, the second data received from the memory controller, and

transmit the second data stored in the buffer to the memory controller upon receiving a read command for the second data from the memory controller.

7. The memory system according to claim 1 , wherein the nonvolatile memory includes a plurality of memory chips, each of which is capable of turning-on/off of an on-die termination (ODT) function, and

the memory interface circuit is further connected to each memory chip in a one-to-one correspondence with an ODT control signal line and is further configured to turn on/off the ODT function of each memory chip by operating the ODT control signal line.

8. The memory system according to claim 1 , wherein the nonvolatile memory includes a plurality of blocks, and

the memory interface circuit is further configured to execute periodical read process for each of the plurality of blocks.

9. The memory system according to claim 1 , wherein the memory interface circuit is free of an interface connected to the host.

10. The memory system according to claim 1 , wherein the memory interface circuit and the nonvolatile memory are both enclosed in the second package.

11. The memory system according to claim 1 , wherein (1) an interface connection between the memory interface circuit and the memory controller and (2) an interface connection between the memory interface circuit and the nonvolatile memory are compatible with each other.

12. The memory system according to claim 1 , further comprising a first board and a second board, the second board being different from the first board,

wherein the first package is mounted on the first board, and the second package and the nonvolatile memory are both mounted on the second board, the first board and the second board being connected by a connector and/or a cable.

13. A memory system accessible from a host, the memory system comprising:

a nonvolatile memory,

a memory controller included in a first package, and

a memory interface circuit included in a second package, the second package being different from the first package, wherein:

the memory controller includes an encoder for performing encoding for error correction and is configured to:

encode first data into second data using the encoder,

program the second data into a first location in the nonvolatile memory, and

thereafter issue a reprogramming refresh instruction to the memory interface circuit; and

the memory interface circuit is interposed between the nonvolatile memory and the memory controller, includes a decoder for performing decoding for error correction, and is configured to:

read the second data, as third data, from the first location in the nonvolatile memory according to the reprogramming refresh instruction,

correct an error bit included in the third data to generate fourth data by decoding the third data using the decoder, and

reprogram, without erasing, the fourth data in the first location in the nonvolatile memory.

14. The memory system according to claim 13 , wherein the memory interface circuit is further configured to:

read fifth data from a second location in the nonvolatile memory,

diagnose the fifth data, and

convey a result of the diagnosis to the memory controller, and

the memory controller is further configured to issue the reprogramming refresh instruction on the basis of the conveyed result of the diagnosis.

15. The memory system according to claim 14 , wherein the nonvolatile memory includes a plurality of memory cells, each of the plurality of memory cells holds a threshold voltage corresponding to a value among a plurality of values,

the memory interface circuit is further configured to:

acquire a margin width on the basis of a number of error bits in the fifth data, and

convey the acquired margin width to the memory controller as the result of the diagnosis; and

the memory controller is further configured to issue the reprogramming refresh instruction on the basis of a comparison between the margin width and a first threshold value.

16. The memory system according to claim 13 , wherein the memory interface circuit is further configured to:

read data from a location in the nonvolatile memory a plurality of times with different read voltages as a plurality of pieces of sixth data,

acquire soft bit information on the basis of the plurality of pieces of the sixth data, and

input the acquired soft bit information to the decoder for execution of error correction.

17. The memory system according to claim 13 , wherein the memory interface circuit is free of an interface connected to the host.

18. The memory system according to claim 14 , wherein the memory controller includes a second decoder and is further configured to issue the reprogramming refresh instruction or execute a normal refresh on the basis of the result of the diagnosis, and

the normal refresh includes reading seventh data from a third location in the nonvolatile memory, correcting an error bit included in the seventh data using the second decoder to generate eighth data, and programming the eighth data into a fourth location in the nonvolatile memory, the fourth location being different from the third location.

19. The memory system according to claim 14 , wherein the memory interface circuit is further configured to convey the number of error bits included in the fifth data to the memory controller as the result of the diagnosis, and

the memory controller is further configured to issue the reprogramming refresh instruction on the basis of the number of error bits.