Copper alloy sputtering target and semiconductor element wiring
A first copper alloy sputtering target comprising 0.5 to 4.0 wt % of Al and 0.5 wtppm or less of Si and a second copper alloy sputtering target comprising 0.5 to 4.0 wt % of Sn and 0.5 wtppm or less of Mn are disclosed. The first and/or the second alloy sputtering target can further comprise one or more elements selected from among Sb, Zr, Ti, Cr, Ag, Au, Cd, In and As in a total amount of 1.0 wtppm or less. A semiconductor element wiring formed by the use of the above targets is also disclosed. The above copper alloy sputtering target allows the formation of a wiring material for a semiconductor element, in particular, a seed layer being stable, uniform and free from the occurrence of coagulation during electrolytic copper plating and exhibits excellent sputtering film formation characteristics.
1. A semiconductor element, comprising:
a substrate providing a wiring groove;
a diffusion barrier layer coating said wiring groove, said diffusion barrier layer being a film of Ta, a Ta alloy, or a nitride thereof;
a seed layer made of copper alloy deposited via sputtering deposition on said diffusion barrier layer, said seed layer being made of a copper alloy containing 0.5 to 4.0 wt % of Al and an amount of Si content of 0.19 wtppm or more and 0.5 wtppm or less to improve oxidation resistance; and
a layer of copper electrodeposited on said seed layer to provide wiring.
2. A semiconductor element according to claim 1 , wherein said copper alloy seed layer further contains one or more additional elements selected from the group consisting of Sb, Zr, Ti, Cr, Ag, Au, Cd, In and As.
3. A method of making a semiconductor element, comprising the steps of:
forming a copper alloy seed layer via sputtering deposition on a diffusion barrier layer coating a wiring groove on a substrate, the sputtering deposition of the seed layer being performed with a sputtering target made of a copper alloy containing 0.5 to 4.0 wt % of Al and 0.5 wtppm or less of Si and having an average crystal grain size of 0.1 to 60 μm and an average crystal grain size variation of within ±20%; and
electroplating a layer of copper on the seed layer to form copper wiring;
said copper alloy seed layer being made of a copper alloy containing 0.5 to 4.0 wt % of Al and an amount of Si content of 0.19 wtppm or more and 0.5 wtppm or less to improve oxidation resistance; and
said diffusion barrier layer being a film of Ta, a Ta alloy, or a nitride thereof.
4. A method according to claim 3 , wherein said copper alloy seed layer contains both Al and Sn, and wherein a total amount of Al and Sn contained in said copper alloy is 0.5 to 4.0 wt %.
5. A method according to claim 3 , wherein said copper alloy seed layer further contains one or more additional elements selected from the group consisting of Sb, Zr, Ti, Cr, Ag, Au, Cd, In and As.
6. A method according to claim 3 , wherein said amount of Si in said copper alloy seed layer is 0.19 wtppm or more and 0.41 wtppm or less.
7. A semiconductor element according to claim 1 , wherein said copper alloy seed layer contains 0.5 to 4.0 wt % of Al and an amount of Si content of 0.19 wtppm or more and 0.41 wtppm or less to improve oxidation resistance.