Three-dimensional semiconductor device

1. A three-dimensional semiconductor device, comprising:

gate electrodes including pad regions sequentially lowered by a first step portion in a first direction and sequentially lowered by a second step portion in a second direction perpendicular to the first direction, the second step portion being lower than the first step portion,

wherein a length of a single pad region among pad regions sequentially lowered by the second step portion in the second direction is less than a length of a remainder of the pad regions in the second direction,

wherein a pad region of the pad regions adjacent to the single pad region in the second direction is separated into a pad portion and a dummy portion adjacent to each other in the second direction, the pad portion and the dummy portion including at least one same material,

wherein a length in the second direction of the pad portion is greater than a length in the second direction of the dummy portion, and

wherein the pad portion is spaced apart from the dummy portion.

2. The three-dimensional semiconductor device as claimed in claim 1 ,

wherein the gate electrodes include a first gate electrode having a first pad region, a second gate electrode having a second pad region, a third gate electrode having a third pad region, and a fourth gate electrode having a fourth pad region,

wherein the first pad region, the second pad region, the third pad region, and the fourth pad region are arrayed to have a stepped shape sequentially lowered by the second step portion in the second direction, and

wherein a length of the third pad region is less than a length of a single pad region among the first pad region, the second pad region, and the fourth pad region in the second direction.

3. A three-dimensional semiconductor device, comprising:

a first main separation structure and a second main separation structure in a memory cell array region and in a connection region of a substrate;

a first secondary separation structure between the first main separation structure and the second main separation structure; and

gate electrodes stacked in the memory cell array region in a direction perpendicular to a surface of the substrate and extended to the connection region, the gate electrodes being between the first main separation structure and the second main separation structure,

wherein the gate electrodes include pad regions sequentially lowered by a first step portion in a first direction oriented from the memory cell array region toward the connection region, and sequentially lowered by a second step portion in a second direction oriented from the first main separation structure to the second main separation structure, the second step portion being lower than the first step portion,

wherein contact plugs are positioned on the pad regions, pad regions sequentially lowered by the second step portion in the second direction including a single pad region,

wherein the first secondary separation structure divides the single pad region into a pad portion and a dummy portion,

wherein the contact plugs include a single contact plug on the single pad region, and

wherein the single contact plug is in contact with the pad portion and is spaced apart from the dummy portion.

4. The three-dimensional semiconductor device as claimed in claim 3 , further comprising one or more upper gate electrodes on the gate electrodes,

wherein the one or more upper gate electrodes are provided in plural, and the upper gate electrodes provided in plural include a plurality of upper pad regions sequentially lowered in the first direction and disposed on a same level in the second direction, and

wherein a length in the first direction of a single upper pad region among the plurality of upper pad regions is greater than a length in the first direction of each of pad regions of the gate electrodes.

5. The three-dimensional semiconductor device as claimed in claim 3 , further comprising one or more lower gate electrodes under the gate electrodes,

wherein the one or more lower gate electrodes are disposed in plural,

wherein a lowermost lower gate electrode among the one or more lower gate electrodes provided in plural includes a lower select pad region, and

wherein a length in the first direction of the lower select pad region is greater than a length in the first direction of the pad regions of the gate electrodes,

wherein the one or more lower gate electrodes provided in plural include a plurality of lower electrodes on the lowermost lower gate electrode,

wherein the plurality of lower electrodes include lower pad regions sequentially lowered by the second step portion in the first direction, and

wherein a length in the first direction of a single lower pad region among the lower pad regions of the plurality of lower electrodes is different from a length in the first direction of a remainder of the lower pad regions sequentially lowered by the second step portion in the first direction.

6. The three-dimensional semiconductor device as claimed in claim 3 , further comprising a second secondary separation structure between the first main separation structure and the second main separation structure,

wherein the first secondary separation structure is in the connection region, and

wherein the second secondary separation structure is on the memory cell array region, and extended to a portion of the connection region, and

wherein the second secondary separation structure has an end portion opposing an end portion of the first secondary separation structure.

7. The three-dimensional semiconductor device as claimed in claim 6 , wherein:

the pad regions include a first pad region, a second pad region, a third pad region, and a fourth pad region, sequentially lowered by the second step portion in the second direction, and

wherein a length in the second direction of the third pad region is less than a length in the second direction of each of the first pad region, the second pad region, and the fourth pad region, and

wherein the contact plugs include a first contact plug on the first pad region, a second contact plug on the second pad region, a third contact plug on the third pad region, and a fourth contact plug on the fourth pad region,

wherein the second pad region is the single pad region,

wherein the second contact plug is the single contact plug, and

wherein at least a portion of the dummy portion is between the pad portion and the third contact plug.

8. The three-dimensional semiconductor device as claimed in claim 7 , wherein:

the first secondary separation structure intersects the second pad region and divides the second pad region into the pad portion and the dummy portion,

each of the gate electrodes includes a first conductive material and a second conductive material, different from each other, and

the pad portion and the dummy portion are formed of the first conductive material and the second conductive material.

9. The three-dimensional semiconductor device as claimed in claim 7 , wherein;

the first secondary separation structure intersects the second pad region and divides the second pad region into the pad portion and the dummy portion,

each of the gate electrodes includes a first conductive material and a second conductive material, different from each other,

the pad portion and the dummy portion commonly include the first conductive material, and

the pad portion includes a larger amount of the second conductive material than the dummy portion.

10. The three-dimensional semiconductor device as claimed in claim 6 , further comprising a gate dielectric covering a lower surface and an upper surface of each of the gate electrodes and covering a single side surface of each of the gate electrodes, the first secondary separation structure allows a portion of the gate dielectric to be separated.

11. The three-dimensional semiconductor device as claimed in claim 3 , further comprising:

edge gate electrodes opposing the gate electrodes; and

sacrificial layers opposing the edge gate electrodes and thicker than the edge gate electrodes, the edge gate electrodes being between the sacrificial layers and the second main separation structure,

wherein the second main separation structure is disposed between the gate electrodes and the edge gate electrodes.

12. A three-dimensional semiconductor device, comprising: gate electrodes including intermediate pad regions lowered by a first step portion in a first direction and lowered by a second step portion in a second direction perpendicular to the first direction, the second step portion being lower than the first step portion,

wherein pad regions sequentially lowered by the second step portion in the second direction include upper pad region, lower pad region and intermediate pad regions between the upper pad region and the lower pad region, and

wherein a length in the second direction of at least one of the intermediate pad regions is different from a length in the second direction of at least one of the upper pad region and the lower pad region.

13. The three-dimensional semiconductor device as claimed in claim 3 , wherein the length in the second direction of the single pad region is greater than a length in the second direction of at least one of a remainder of the pad regions sequentially lowered by the second step portion in the second direction.

14. The three-dimensional semiconductor device as claimed in claim 3 ,

wherein the pad portion is spaced apart from dummy portion,

wherein a length in the first direction of the pad portion is the same as a length in the first direction of the dummy portion, and

wherein a length in the second direction of the pad portion is greater than a length in the second direction of the dummy portion.

15. The three-dimensional semiconductor device as claimed in claim 3 ,

wherein the gate electrodes include a single gate electrode,

wherein the single gate electrode includes a gate region, the pad portion and the dummy portion,

wherein the pad portion and the dummy portion extend from the gate region of the single gate electrode, and

wherein a thickness of each of the pad portion and the dummy portion is greater than a thickness of the gate region of the single gate electrode.

16. The three-dimensional semiconductor device as claimed in claim 12 ,

wherein the intermediate pad regions include a first intermediate pad region and a second intermediate pad region,

wherein the length in the second direction of the first intermediate pad regions is greater than the length in the second direction of the at least one of the upper pad region and the lower pad region, and

wherein the length in the second direction of the second intermediate pad regions is smaller than the length in the second direction of the at least one of the upper pad region and the lower pad region.

17. The three-dimensional semiconductor device as claimed in claim 12 ,

wherein the intermediate pad regions include a first intermediate pad region and a second intermediate pad region,

wherein the upper pad region, the first intermediate pad region, the second intermediate pad region, and the lower pad region are arrayed to have a stepped shape sequentially lowered by the second step portion in the second direction,

wherein the length in the second direction of the first intermediate pad region is greater than the length in the second direction of the second intermediate pad region,

wherein a length in the second direction of the first intermediate pad region is greater than the length in the second direction of the at least one of the upper pad region and the lower pad region, and

wherein a length in the second direction of the second intermediate pad region is smaller than the length in the second direction of the at least one of the upper pad region and the lower pad region.

18. The three-dimensional semiconductor device as claimed in claim 12 , further comprising a separation structure; and

contact plugs on the pad regions,

wherein the intermediate pad regions include a first intermediate pad region and a second intermediate pad region,

wherein the gate electrodes include a single gate electrode,

wherein the single gate electrode includes a gate region and the first intermediate pad region,

wherein the contact plugs include an upper contact plug on the upper pad region, a first intermediate contact plug on the first intermediate pad region, a second intermediate contact plug on the second intermediate pad region, and a lower contact plug on the lower pad region,

wherein the separation structure divides the first intermediate pad region into a pad portion and a dummy portion, and

wherein the first intermediate contact plug is in contact with the pad portion and is spaced apart from the dummy portion.

19. The three-dimensional semiconductor device as claimed in claim 18 , wherein the upper pad region, the first intermediate pad region, the second intermediate pad region, and the lower pad region are arrayed to have a stepped shape sequentially lowered by the second step portion in the second direction, and

wherein at least a portion of the dummy portion is between the pad portion and the second intermediate contact plug.

20. The three-dimensional semiconductor device as claimed in claim 1 , further comprising a contact plug on the pad region,

wherein the contact plug is in contact with the pad portion and is spaced apart from the dummy portion.