Semiconductor memory device including a substrate, various interconnections, semiconductor member, charge storage member and a conductive member
According to one embodiment, a semiconductor memory device includes: a substrate; a first interconnect; a second interconnect; a plurality of third interconnects; a fourth interconnect; a semiconductor member; a charge storage member; and a conductive member. One of the plurality of third interconnects is disposed on two second-direction sides of the conductive member. Portions of the one of the plurality of third interconnects disposed on the two second-direction sides of the conductive member are formed as one body.
1. A semiconductor memory device, comprising:
a substrate;
a peripheral circuit on the substrate;
a plurality of first wirings provided above the peripheral circuit and arranged to be separated from each other along a first direction perpendicular to a surface of the substrate;
a first semiconductor member extending in the first direction;
a first charge storage member provided between the first semiconductor member and one of the plurality of first wirings;
a second wiring provided between the peripheral circuit and the plurality of first wirings in the first direction, the second wiring being connected with the first semiconductor member; and
first and second conductive members extending in the first direction and connected with the peripheral circuit, the plurality of first wirings and the second wiring surrounding each of the first and second conductive members.
2. The semiconductor memory device according to claim 1 , further comprising:
a second semiconductor member extending in the first direction and connected with the second wiring; and
a second charge storage member provided between the second semiconductor member and one of the plurality of first wirings,
the first and second conductive members being provided between the first semiconductor member and the second semiconductor member in a second direction crossing the first direction.
3. The semiconductor memory device according to claim 1 , further comprising:
a third wiring provided between the peripheral circuit and the second wiring and directly connected with the first conductive member.
4. The semiconductor memory device according to claim 3 , wherein
the peripheral circuit includes a transistor and the third wiring electrically connected with the transistor.
5. The semiconductor memory device according to claim 3 , further comprising:
a fourth wiring provided above the plurality of first wirings and directly connected with the first conductive member.
6. The semiconductor memory device according to claim 5 , further comprising:
a fifth wiring provided between the substrate and the third wiring; and
a first via directly connected with the third wiring and the fifth wiring.
7. The semiconductor memory device according to claim 6 , further comprising:
a sixth wiring provided between the substrate and the fifth wiring;
a second via directly connected with the fifth wiring and the sixth wiring; and
a third via directly connected with a transistor of the peripheral circuit.
8. A semiconductor memory device, comprising:
a substrate;
a peripheral circuit on the substrate;
a plurality of first wirings provided above the peripheral circuit and arranged to be separated from each other along a first direction perpendicular to a surface of the substrate;
a first semiconductor member extending in the first direction;
a first charge storage member provided between the first semiconductor member and one of the plurality of first wirings;
a second wiring provided between the peripheral circuit and the plurality of first wirings in the first direction, the second wiring being connected with the first semiconductor member; and
a first conductive member extending in the first direction and connected with the peripheral circuit; and
a second conductive member extending in the first direction and connected with the peripheral circuit,
a part of the plurality of first wirings being provided between the first conductive member and the second conductive member.
9. The semiconductor memory device according to claim 8 , further comprising:
a second semiconductor member extending in the first direction; and
a second charge storage member provided between the second semiconductor member and one of the plurality of first wirings,
the first and second conductive members being provided between the first semiconductor member and the second semiconductor member in a second direction crossing the first direction.
10. The semiconductor memory device according to claim 8 , further comprising:
a third wiring provided between the peripheral circuit and the second wiring and directly connected with the first conductive member.
11. The semiconductor memory device according to claim 10 , wherein
the peripheral circuit includes a transistor, and
the third wiring is electrically connected with the transistor.
12. The semiconductor memory device according to claim 10 , further comprising:
a fourth wiring provided above the plurality of first wirings and directly connected with the first conductive member.
13. The semiconductor memory device according to claim 12 , further comprising:
a fifth wiring provided between the substrate and the third wiring; and
a first via extending in the first direction and directly connected with the third wiring and the fifth wiring.
14. The semiconductor memory device according to claim 13 , further comprising:
a sixth wiring provided between the substrate and the fifth wiring;
a second via extending in the first direction and directly connected with the fifth wiring and the sixth wiring; and
a third via extending in the first direction and directly connected with the sixth wiring and a transistor of the peripheral circuit.
15. A semiconductor memory device, comprising:
a substrate;
a peripheral circuit on the substrate;
a first memory cell region, a contact region, and a second memory cell region provided above the peripheral circuit, the contact region being provided between the first memory cell region and the second memory cell region in a first direction parallel to a surface of the substrate;
a plurality of first wirings arranged to be separated from each other along a second direction perpendicular to the surface of the substrate in the contact region;
first and second conductive members extending in the second direction and connected with the peripheral circuit in the contact region, the plurality of first wirings surrounding each of the first and second conductive members.
16. The semiconductor memory device according to claim 15 , further comprising:
a first semiconductor member extending in the second direction in the first memory cell region;
a plurality of second wirings arranged to be separated from each other along the second direction in the first memory cell region; and
a first charge storage member provided between the first semiconductor member and one of the plurality of second wirings.
17. The semiconductor memory device according to claim 15 , wherein
the plurality of first wirings are provided in the first memory cell region and the second memory cell region.
18. The semiconductor memory device according to claim 15 , further comprising:
a fourth wiring provided between the peripheral circuit and the plurality of first wirings and directly connected with the first conductive member.
19. The semiconductor memory device according to claim 16 , further comprising:
a second semiconductor member extending in the second direction in the second memory cell region;
a plurality of third wirings arranged to be separated from each other along the second direction in the second memory cell region; and
a second charge storage member provided between the second semiconductor member and one of the plurality of second wirings.
20. The semiconductor memory device according to claim 19 , wherein
one of the plurality of first wirings, one of the plurality of second wirings, and one of the plurality of third wirings are electrically shared.
21. The semiconductor memory device according to claim 18 , wherein
the peripheral circuit includes a transistor, and
the fourth wiring is electrically connected with the transistor.
22. The semiconductor memory device according to claim 18 , further comprising:
a fifth wiring provided above the plurality of first wirings and directly connected with the first conductive member.
23. The semiconductor memory device according to claim 22 , further comprising:
a sixth wiring provided between the substrate and the fourth wiring; and
a first via extending in the second direction and directly connected with the fourth wiring and the sixth wiring.
24. The semiconductor memory device according to claim 23 , further comprising:
a seventh wiring provided between the substrate and the sixth wiring;
a second via extending in the second direction and directly connected with the sixth wiring and the seventh wiring; and
a third via extending in the second direction and directly connected with the seventh wiring and a transistor of the peripheral circuit.
25. A semiconductor memory device, comprising:
a substrate;
a peripheral circuit on the substrate;
a first memory cell region, a contact region, and a second memory cell region provided above the peripheral circuit, the contact region being provided between the first memory cell region and the second memory cell region in a first direction parallel to a surface of the substrate;
a plurality of first wirings arranged to be separated from each other along a second direction perpendicular to the surface of the substrate in the contact region;
a first conductive member extending in the second direction and connected with the peripheral circuit; and
a second conductive member extending in the second direction and connected with the peripheral circuit,
a part of the plurality of first wirings being provided between the first conductive member and the second conductive member.
26. The semiconductor memory device according to claim 25 , further comprising:
a first semiconductor member extending in the second direction in the first memory cell region;
a plurality of second wirings arranged to be separated from each other along the second direction in the first memory cell region; and
a first charge storage member provided between the first semiconductor member and one of the plurality of second wirings.
27. The semiconductor memory device according to claim 25 , wherein
the plurality of first wirings are provided in the first memory cell region and the second memory cell region.
28. The semiconductor memory device according to claim 25 , further comprising:
a fourth wiring provided between the peripheral circuit and the plurality of first wirings and directly connected with the first conductive member.
29. The semiconductor memory device according to claim 26 , further comprising:
a second semiconductor member extending in the second direction in the second memory cell region;
a plurality of third wirings arranged to be separated from each other along the second direction in the second memory cell region; and
a second charge storage member provided between the second semiconductor member and one of the plurality of third wirings.
30. The semiconductor memory device according to claim 29 , wherein
one of the plurality of first wirings, one of the plurality of second wirings, and one of the plurality of third wirings are electrically shared.
31. The semiconductor memory device according to claim 28 , wherein
the peripheral circuit includes a transistor, and
the fourth wiring is electrically connected with the transistor.
32. The semiconductor memory device according to claim 31 , further comprising:
a fifth wiring provided above the plurality of first wirings and directly connected with the first conductive member.
33. The semiconductor memory device according to claim 32 , further comprising:
a sixth wiring provided between the substrate and the fourth wiring; and
a first via extending in the second direction and directly connected with the fourth wiring and the sixth wiring.
34. The semiconductor memory device according to claim 33 , further comprising:
a seventh wiring provided between the substrate and the sixth wiring;
a second via extending in the second direction and directly connected with the sixth wiring and the seventh wiring; and
a third via extending in the second direction and directly connected with the seventh wiring and a transistor of the peripheral circuit.