Magnetic random access memory structure and manufacturing method of the same
View Patent ↗The present disclosure provides a magnetic random access memory structure, including an array region, and a logic region adjacent to the array region. The logic region includes a bottom electrode via, a magnetic tunneling junction layer over the bottom electrode via, a top electrode over the MTJ, a conformable oxide layer over the MTJ and the top electrode, and a silicon oxide layer over the conformable oxide layer. The conformable oxide layer and the silicon oxide layer extend from the array region to the logic region.
1. A method for manufacturing a magnetic random access memory (MRAM) structure, the method comprising:
forming a magnetic tunneling junction (MTJ) structure in an array region;
forming a protection layer over the MTJ structure in the array region and in a logic region adjacent to the array region;
removing the protection layer in the logic region;
forming a conformable oxide layer in the array region and the logic region;
forming a low-k dielectric layer over the conformable oxide layer in the array region and the logic region;
forming a dielectric stack over the low-k dielectric layer in the array region and the logic region;
forming an anti-reflective coating (ARC) over the dielectric stack in the array region and the logic region; and
performing an ARC etch back and stopping the etch at the dielectric stack in the array region and the logic region.
2. The method of claim 1 , wherein the ARC etch back stops at a first etch stop layer of the dielectric stack contacting the low-k dielectric layer.
3. The method of claim 2 , further comprising:
performing a planarization operation over the logic region and the array region thereby exposing the low-k dielectric layer in the array region; and
stopping the planarization operation at the dielectric stack in the logic region.
4. The method of claim 3 , wherein the planarization operation stops at a second etch stop layer above the first etch stop layer of the dielectric stack.
5. The method of claim 3 , further comprising simultaneously forming via trenches in the array region and the logic region.
6. The method of claim 5 , wherein forming the via trenches in the array region comprises removing a portion of the conformable oxide layer and a portion of the protection layer.
7. The method of claim 5 , wherein forming the via trenches in the logic region comprises removing a portion of the conformable oxide layer.
8. A method for manufacturing a magnetic random access memory (MRAM) structure, the method comprising:
forming a magnetic tunneling junction (MTJ) structure in an array region;
forming a protection layer over the MTJ structure in the array region and in a logic region adjacent to the array region;
removing the protection layer in the logic region;
forming a low-k dielectric layer over the array region and the logic region;
forming a dielectric stack over the low-k dielectric layer in the array region and in a logic region adjacent to the array region; and
forming via trenches over the logic region and over the MTJ structure in the array region simultaneously.
9. The method of claim 8 , wherein the via trench in the array region reaches a top surface of a top electrode over the MTJ structure.
10. The method of claim 8 , wherein the via trench in the logic region reaches a top surface of a metal line in the logic region.
11. The method of claim 8 , further comprising forming a conformable oxide layer in the array region and the logic region prior to forming the low-k dielectric layer.
12. The method of claim 11 , wherein forming the via trenches in the array region comprises removing a portion of the conformable oxide layer and a portion of the protection layer.
13. A method for manufacturing a magnetic random access memory (MRAM) structure, the method comprising:
forming a magnetic tunneling junction (MTJ) structure in an array region;
forming a low-k dielectric layer over the MTJ structure in the array region and a logic region adjacent to the array region;
forming a dielectric stack over the low-k dielectric layer in the array region and the logic region, wherein forming the dielectric stack comprises:
forming a first etch stop layer; and
forming a second etch stop layer over the first etch stop layer, wherein the second etch stop layer is different from the first etch stop layer;
forming an anti-reflective coating (ARC) over the dielectric stack in the array region and the logic region; and
performing an ARC etch back and stopping the etch at the first etch stop layer in the array region.
14. The method of claim 13 , further comprising:
forming a spacer over the MTJ structure;
forming a protection layer over the spacer; and
forming a conformable oxide layer over the logic region and the array region.
15. The method of claim 14 , further comprising simultaneously forming via trenches in the array region and the logic region after the planarization operation.
16. The method of claim 15 , wherein forming the via trenches in the array region comprises removing a portion of the conformable oxide layer, a portion of the protection layer, and a portion of the spacer.
17. The method of claim 15 , wherein forming via trenches in the logic region comprises removing a portion of the conformable oxide layer and a portion of the low-k dielectric layer.
18. The method of claim 13 , wherein:
the low-k dielectric layer has a first selectivity;
the first etch stop layer has a second selectivity, wherein the first selectivity is greater than the second selectivity in the ARC etch back operation; and
the second etch stop layer is for a planarization operation over the first etch stop layer, the second etch stop layer has a third selectivity, and the first selectivity is greater than the third selectivity in the planarization operation.
19. The method of claim 13 , wherein the first etch stop layer comprises oxide.
20. The method of claim 13 , wherein the second etch stop layer comprises oxynitrides.