Method of manufacturing MRAM device between adjacent metal line layers and MRAM device
A method of manufacturing a semiconductor device includes: forming a substrate over the substrate, the substrate defining a logic region and a memory region; depositing a bottom electrode layer across the logic region and the memory region; depositing a magnetic tunnel junction (MTJ) layer over the bottom electrode layer; depositing a first conductive layer over the MTJ layer; depositing a sacrificial layer over the first conductive layer; etching the sacrificial layer in the memory region to expose the first conductive layer in the memory region while keeping the first conductive layer in the logic region covered; depositing a second conductive layer in the memory region and the logic region; patterning the second conductive layer to expose the MTJ layer in the memory region; and etching the patterned second conductive layer and the MTJ layer to form a top electrode and an MTJ, respectively, in the memory region.
1 . A semiconductor device, comprising:
a substrate, the semiconductor device defining a memory region and a logic region; and
a memory device arranged in the memory region over the substrate, the memory device comprising:
a bottom electrode via arranged over the substrate;
a bottom electrode arranged over the bottom electrode via;
a magnetic tunneling junction (MTJ) arranged over the bottom electrode;
a top electrode arranged over the MTJ, the top electrode comprising an upper portion and a lower portion separated from the upper portion by an interface region having a thickness between 1 Å and 5 Å, the thickness of the interface region is smaller than the upper portion and the lower portion;
a first metal line having a first height is disposed over and in contact with the top electrode in the memory region, wherein the first height is a first distance between a bottommost surface of the first metal line and an uppermost surface of the first metal line; and
a second metal line in the logic region comprises a second height that is greater than the first height, wherein the second height is a second distance between a bottommost surface of the second metal line and an uppermost surface of the second metal line,
wherein the bottom electrode via is trapezoid shaped, and
wherein a longer parallel side of the trapezoid faces the bottom electrode.
2 . The semiconductor device according to claim 1 , wherein the interface region between the upper portion and the lower portion comprises an oxide form of the lower portion.
3 . The semiconductor device according to claim 1 , wherein the interface region includes a metal oxide.
4 . The semiconductor device according to claim 1 , wherein the bottom electrode via includes a conductive material selected from the group consisting of Cu, TiN, TaN, and Ta.
5 . The semiconductor device according to claim 1 , wherein the longer parallel side of the trapezoid is wider than a side of the bottom electrode facing the bottom electrode via.
6 . The semiconductor device according to claim 1 , wherein the bottom electrode includes a conductive material selected from the group consisting of TiN, TaN, Ti, Ta, and Ru.
7 . The semiconductor device according to claim 1 , wherein the bottom electrode is wider than the top electrode.
8 . The semiconductor device according to claim 1 , wherein the top electrode, MTJ, and bottom electrode are trapezoid shaped.
9 . The semiconductor device according to claim 1 , further comprising sidewall spacers disposed on sidewalls of the MTJ.
10 . The semiconductor device according to claim 1 , further comprising a lining layer disposed between the substrate and bottom electrode via.
11 . The semiconductor device according to claim 10 , wherein the lining layer includes a conductive layer selected from the group consisting of Cu, TaN, and Ta.
12 . A semiconductor device, comprising:
a substrate, the semiconductor device defining a memory region and a logic region; and
a memory device arranged in the memory region over the substrate, the memory device comprising:
a bottom electrode via arranged over the substrate;
a bottom electrode arranged over the bottom electrode via;
a magnetic tunneling junction (MTJ) arranged over the bottom electrode; and
a top electrode arranged over the MTJ, the top electrode comprising a lower portion adjacent the MTJ, an interface region having a thickness between 1 Å and 5 Å on the lower portion, and an upper portion on the interface region, the thickness of the interface region is smaller than the upper portion and the lower portion;
a first metal line having a first height is disposed over and in contact with the top electrode in the memory region, wherein the first height is a first distance between a bottommost surface of the first metal line and an uppermost surface of the first metal line; and
a second metal line in the logic region comprises a second height that is greater than the first height, wherein the second height is a second distance between a bottommost surface of the second metal line and an uppermost surface of the second metal line,
wherein the top electrode, the MTJ, and bottom electrode are trapezoid shaped, and
wherein a longer parallel side of the trapezoid is the bottom electrode and the shorter parallel side of the trapezoid is the top electrode.
13 . The semiconductor device of claim 12 , wherein the bottom electrode via is trapezoid shaped.
14 . The semiconductor device of claim 12 , wherein the bottom electrode includes a conductive material selected from the group consisting of TiN, TaN, Ti, Ta, and Ru.
15 . The semiconductor device of claim 12 , further comprising silicon nitride spacers disposed on sidewalls of the MTJ.
16 . A semiconductor device, comprising:
a substrate, the semiconductor device defining a memory region and a logic region; and
a memory device arranged in the memory region over the substrate, the memory device comprising:
a bottom electrode via on a lining layer arranged over the substrate, the lining layer comprising a conductive layer selected from the group consisting of Cu, TaN, and Ta;
a bottom electrode arranged over the bottom electrode via;
a magnetic tunneling junction (MTJ) arranged over the bottom electrode; and
a top electrode arranged over the MTJ, the top electrode comprising a lower portion adjacent the MTJ, an interface region having a thickness between 1 Å and 5 Å on the lower portion, and an upper portion on the interface region, the thickness of the interface region is smaller than the upper portion and the lower portion;
a first metal line is disposed over and in contact with the top electrode;
a second metal line in the logic region comprises a second height that is greater than a first height of the first metal line, wherein the first height is a first distance between a bottommost surface of the first metal line and an uppermost surface of the first metal line, and the second height is a second distance between a bottommost surface of the second metal line and an uppermost surface of the second metal line,
wherein the bottommost surface of the first metal line is at a same level as an uppermost surface of the upper portion of the top electrode.
17 . The semiconductor device of claim 16 , wherein the MTJ is trapezoid shaped.
18 . The semiconductor device of claim 16 , further comprising silicon nitride spacers disposed on sidewalls of the MTJ.
19 . The semiconductor device of claim 16 , wherein the bottom electrode via is trapezoid shaped.
20 . The semiconductor device of claim 19 , wherein a longer parallel side of the trapezoid shaped bottom electrode via faces the bottom electrode.