Semiconductor structure and method of forming the same
The present disclosure provides a semiconductor structure, including a memory region and a logic region adjacent to the memory region. The memory region includes a first N th metal line, a first stop layer being disposed over a magnetic tunneling junction (MTJ) over the first N th metal line, and a first (N+1) th metal via being disposed over the MTJ and surrounded by the first stop layer, the first (N+1) th metal via having a first height. The logic region includes a second N th metal line, a second stop layer being disposed over an (N+1) th metal line, and a second (N+1) th metal via over the (N+1) th metal line and having a second height. N is an integer greater than or equal to 1 and the first height is greater than the second height. A method of manufacturing the semiconductor structure is also disclosed.
1. A semiconductor structure, comprising:
a transistor layer;
a memory region over the transistor layer, comprises:
a first N th metal line;
a first stop layer being disposed over a magnetic tunneling junction (MTJ) over the first N th metal line; and
a first (N+1) th metal via being disposed over the MTJ and surrounded by the first stop layer, the first (N+1) th metal via having a first height; and
a logic region adjacent to the memory region, the logic region comprises:
a second N th metal line;
a second stop layer being disposed over an (N+1) th metal line; and
a second (N+1) th metal via over the (N+1) th metal line and having a second height;
wherein N is an integer greater than or equal to 1, the first height is greater than the second height, and a vertical distance between the second stop layer and the transistor layer is greater than a vertical distance between the first stop layer and the transistor layer.
2. The semiconductor structure of claim 1 , wherein the MTJ being disposed between a bottom electrode and a top electrode in the memory region.
3. The semiconductor structure of claim 2 , further comprising a cap positioned between the first stop layer and the top electrode.
4. The semiconductor structure of claim 3 , wherein a ratio of a width of the cap and a width of a bottom surface of the MTJ is in a range of from about 1.2 to about 2.
5. The semiconductor structure of claim 3 , wherein the cap is composed of Ti, Ta, TiN, TaN, W, Ru or combinations thereof.
6. The semiconductor structure of claim 1 , wherein the first stop layer and the second stop layer are non-coplanar.
7. The semiconductor structure of claim 1 , wherein the first stop layer and the second stop layer are composed of SiC, SiN, SiOC, SiON or combinations thereof.
8. The semiconductor structure of claim 1 , wherein a bottom surface of the second (N+1) th metal via is laterally within the first height.
9. A semiconductor structure, comprising:
a memory region, comprises:
a first N th metal line;
a first stop layer being disposed over a top electrode of a magnetic tunneling junction (MTJ) over the first N th metal line;
a first (N+1) th metal via over the MTJ and surrounded by the first stop layer; and
a cap positioned between the first stop layer and the top electrode; and
a logic region adjacent to the memory region, the logic region comprises:
a second N th metal line;
a second stop layer, disposed over an (N+1) th metal line; and
a second (N+1) th metal via over the (N+1) th metal line;
wherein N is an integer greater than or equal to 1, the first stop layer is non-coplanar with the second stop layer, and the first stop layer is not extended to the logic region.
10. The semiconductor structure of claim 9 , wherein a bottom surface of the second stop layer is higher than a top surface of the first stop layer by a vertical difference.
11. The semiconductor structure of claim 10 , wherein a ratio of the vertical difference and a thickness of the MTJ is in a range of from about 0.2 to about 2.
12. The semiconductor structure of claim 9 , wherein the first (N+1) th metal via has a first height, the second (N+1) th metal via has a second height, and the first height is greater than the second height.
13. The semiconductor structure of claim 9 , wherein a ratio of a width of the cap and a width of a bottom surface of the MTJ and is in a range of from about 1.2 to about 2.
14. The semiconductor structure of claim 9 , wherein the second stop layer is not extended to the memory region.
15. The semiconductor structure of claim 9 , wherein the first stop layer and the second stop layer are composed of SiC, SiN, SiOC, SiON or combinations thereof.
16. A semiconductor structure, comprising:
a memory region, comprises:
a first N th metal line;
a magnetic tunneling junction (MTJ) over the first N th metal line;
a cap on the MTJ;
a first stop layer being disposed over the cap; and
a first (N+1) th metal via being disposed over the MTJ and surrounded by the first stop layer; and
a logic region adjacent to the memory region, the logic region comprises:
a second N th metal line;
a second stop layer being disposed over an (N+1) th metal line; and
a second (N+1) th metal via over the (N+1) th metal line;
wherein N is an integer greater than or equal to 1, and the first stop layer is not extended to the logic region.
17. The semiconductor structure of claim 16 , wherein the first (N+1) th metal via is partially surrounded by the cap.
18. The semiconductor structure of claim 16 , wherein a top surface of the first (N+1) th metal via is coplanar with a top surface of the (N+1) th metal line.
19. The semiconductor structure of claim 16 , wherein the second stop layer is penetrated by the second (N+1) th metal via.
20. The semiconductor structure of claim 16 , wherein two sidewalls of the first stop layer is aligned with two sidewalls of the cap.