Smart turn-off for gate driver circuit
A circuit for controlling a gate driver includes a delay circuit, a first logic circuit, and a second logic circuit. The delay circuit receives a first turn-off signal and produces a second turn-off signal by delaying an assertion of the first turn-off signal by a freewheeling duration. The first logic circuit receives the first and second turn-off signals and produces a smart turn-off signal by asserting the smart turn-off signal when the first turn-off signal is asserted and the second turn-off signal is not asserted. The second logic circuit receives a restart signal and the smart turn-off signal and produces a smart reset signal by asserting the smart reset signal when the restart signal and the smart turn-off signal are de-asserted, and de-asserting the smart reset signal when one or more of the restart signal and the smart turn-off signal are asserted.
1. A circuit comprising:
a delay circuit having an input coupled to a first turn-off signal and an output producing a second turn-off signal, the delay circuit producing the second turn-off signal by delaying an assertion of the first turn-off signal by a freewheeling duration;
a first logic circuit having first and second inputs respectively coupled to the first and second turn-off signals and an output producing an advanced smart turn-off signal, the first logic circuit asserting the advanced smart turn-off signal when the first turn-off signal is asserted and the second turn-off signal is not asserted; and
a second logic circuit having a first input coupled to a restart signal, a second input coupled to the advanced smart turn-off signal and an output producing an advanced smart reset signal, the second logic circuit asserting the advanced smart reset signal when the restart signal and the advanced smart turn-off signal are de-asserted, and de-asserting the advanced smart reset signal when the restart signal, the advanced smart turn-off signal, or both are asserted.
2. The circuit of claim 1 , further comprising:
a first pulse generator circuit having an input coupled to the restart signal and an output producing a set signal, the first pulse generator circuit outputting a pulse on the set signal in response to an assertion of the restart signal; and
a second pulse generator circuit having an input coupled to the advanced smart reset signal and an output producing a reset signal, the second pulse generator circuit outputting a pulse on the reset signal in response to an assertion of the advanced smart reset signal.
3. The circuit of claim 2 , further comprising:
a first drive circuit having a first drive output, a first input coupled to the set signal, and a second input coupled to the reset signal, the first drive circuit asserting the drive output in response to an assertion of the set signal and de-asserting the drive output in response to an assertion of the reset signal.
4. The circuit of claim 3 , further comprising:
a second drive circuit having a second drive output and an input coupled to the first turn-off signal, the second drive circuit performing a soft turn-off of the second drive output in response to an assertion of the first turn-off signal.
5. The circuit of claim 4 , wherein the first drive output is a high side output of a gate driver circuit, and wherein the second drive output is a low side output of the gate driver circuit.
6. The circuit of claim 5 , further comprising:
a high side switch having a first conduction terminal coupled to a power supply and a control terminal coupled to the high side output of the gate driver circuit; and
a low side switch having a first conduction terminal coupled to second conduction terminal of the high side switch, a second conduction terminal coupled to a ground, and a control terminal coupled to the low side output of the gate driver circuit.
7. The circuit of claim 6 , wherein the high side switch and the low side switch each include a freewheeling diode and one or more of an insulated gate bipolar transistor and a metal oxide semiconductor field effect transistor.
8. The circuit of claim 1 , further comprising:
a third logic circuit having a first input coupled to a control signal, a second input coupled to the second turn-off signal, and an output producing the restart signal, the third logic circuit generating the restart signal according to the control signal when the second turn-off signal is de-asserted, and de-asserting the restart signal when the second turn-off signal is asserted.
9. A circuit comprising:
a first input to receive a control signal;
a second input to receive a first turn-off signal;
a first output to produce a set signal;
a second output to produce a reset signal; and
a delay circuit,
wherein the circuit is configured to:
generate, using the delay circuit, a second turn-off signal according to the first turn-off signal and a freewheeling duration,
produce an advanced smart turn-off signal according to the first turn-off signal and the second turn-off signal;
produce a restart signal according to the control signal and the second turn-off signal,
produce a set pulse on the set signal in response to an assertion of the restart signal, and
produce a reset pulse on the reset signal in response to a de-assertion of the restart signal when the advanced smart turn-off signal is de-asserted, and
produce the reset pulse on the reset signal in response to a de-assertion of the advanced smart turn-off signal when the restart signal is de-asserted.
10. The circuit of claim 9 , wherein the electronic circuit is further configured to:
assert, the freewheeling duration after an assertion of the first turn-off signal, the second turn-off signal in response to the assertion of the first turn-off signal; and
de-assert the second turn-off signal in response to a de-assertion of the first turn-off signal.
11. The circuit of claim 9 , wherein the electronic circuit is further configured to:
assert the advanced smart turn-off signal when the first turn-off signal is asserted and the second turn-off signal is de-asserted, and
de-assert the advanced smart turn-off signal when the first turn-off signal is de-asserted, the second turn-off signal is asserted, or both.
12. The circuit of claim 9 , wherein the electronic circuit is further configured to:
generate the restart signal according to the control signal when the second turn-off signal is de-asserted, and
de-assert the restart signal when the second turn-off signal is asserted.
13. The circuit of claim 9 , further comprising:
a first switch control signal,
wherein the electronic circuit is further configured to:
assert the first switch control signal in response to the set pulse; and
de-assert the first switch control signal in response to the reset pulse.
14. The circuit of claim 13 , further comprising:
a second switch control signal,
wherein the electronic circuit is further configured to perform, in response to the assertion of the first turn-off signal when the second switch control signal is asserted, a soft turn-off of the second switch control signal.
15. A method for controlling a circuit, the method comprising:
producing, using a delay circuit, a second turn-off signal according to a first turn-off signal and a freewheeling duration;
producing, using a first logic circuit, an advanced smart turn-off signal according to the first turn-off signal and the second turn-off signal;
producing, using a second logic circuit, a restart signal according to a control signal and the second turn-off signal;
producing, using a first pulse generation circuit, a set pulse on a set signal in response to an assertion of the restart signal;
producing, using a second pulse generation circuit, a reset pulse on a reset signal in response to a de-assertion of the restart signal when the advanced smart turn-off signal is de-asserted; and
producing, using the second pulse generation circuit, the reset pulse on the reset signal in response to a de-assertion of the advanced smart turn-off signal when the restart signal is de-asserted.
16. The method of claim 15 , further comprising:
asserting, the freewheeling duration after an assertion of the first turn-off signal, the second turn-off signal in response to the assertion of the first turn-off signal; and
de-asserting the second turn-off signal in response to a de-assertion of the first turn-off signal.
17. The method of claim 15 , further comprising:
asserting the advanced smart turn-off signal when the first turn-off signal is asserted and the second turn-off signal is de-asserted; and
de-asserting the advanced smart turn-off signal when the first turn-off signal is de-asserted, the second turn-off signal is asserted, or both.
18. The method of claim 15 , further comprising:
generating the restart signal according to the control signal when the second turn-off signal is de-asserted; and
de-asserting the restart signal when the second turn-off signal is asserted.
19. The method of claim 15 , further comprising:
asserting a first switch control signal in response to the set pulse; and
de-asserting the first switch control signal in response to the reset pulse.
20. The method of claim 19 , further comprising:
performing, in response to the assertion of the first turn-off signal when a second switch control signal is asserted, a soft turn-off of the second switch control signal.