Fan-out semiconductor package

1. A semiconductor package comprising:

a supporting member having a cavity and including a wiring structure connecting a first surface, and a second surface opposing the first surface;

a connection member on the second surface of the supporting member and including a first redistribution layer connected to the wiring structure;

a semiconductor chip on the connection member, in the cavity, and having connection pads connected to the first redistribution layer;

an encapsulant encapsulating the semiconductor chip in the cavity and covering the first surface of the supporting member; and

a second redistribution layer including wiring patterns embedded in the encapsulant, each of the wiring patterns having an exposed surface, and the wiring patterns including at least one wiring pattern having a connection via penetrating through the encapsulant to connect the wiring structure to the at least one wiring pattern,

wherein the at least one wiring pattern includes a connection portion through which the connection via passes, the connection portion having a width greater than a width of the at least one wiring pattern that is adjacent to and extends from the connection portion, and

wherein the connection portion has a hole, and the connection via penetrates through the hole.

2. The semiconductor package of claim 1 , wherein the connection via has an upper surface of which a central portion is recessed.

3. The semiconductor package of claim 1 , wherein a width of a first region of the connection via that connects to the at least one wiring pattern is greater than a width of a second region of the connection via that connects to with the wiring structure.

4. The semiconductor package of claim 1 , wherein the exposed surface includes an upper surface substantially coplanar with a surface of the encapsulant.

5. The semiconductor package of claim 1 , wherein the second redistribution layer further includes an insulating layer having a first surface and a second surface opposing each other, the second surface being in contact with the encapsulant, and

the wiring patterns include a first wiring pattern embedded in the first surface of the insulating layer and a second wiring pattern on the second surface of the insulating layer and embedded in the encapsulant.

6. The semiconductor package of claim 5 , wherein the connection via includes a first connection via that penetrates through the insulating layer and the encapsulant to connect to the first wiring pattern and the second wiring pattern.

7. The semiconductor package of claim 5 ,

wherein the connection via includes a second connection via that penetrates through the insulating layer and the encapsulant to connect to the second wiring pattern and the wiring structure, and

wherein the second connection via is not in direct contact with the first wiring pattern.

8. The semiconductor package of claim 5 , wherein the second redistribution layer includes an interlayer via that penetrates through the insulating layer and connect the first wiring pattern and the second wiring pattern to each other.

9. The semiconductor package of claim 8 , wherein a width of a first portion of the interlayer via in contact with the second wiring pattern is greater than a width of a second portion of the interlayer via in contact with the first wiring pattern.

10. The semiconductor package of claim 9 , wherein the interlayer via has a structure integrated with the second wiring pattern.

11. The semiconductor package of claim 1 , wherein the second redistribution layer has a plurality of first pad regions, and

a first passivation layer having openings exposing the plurality of first pad regions is on a surface of the encapsulant.

12. A semiconductor package comprising:

a supporting member having a cavity and including a wiring structure connecting first and second surfaces opposing each other;

a connection member on the second surface of the supporting member and including a first redistribution layer connected to the wiring structure;

a semiconductor chip on the connection member, in the cavity, and having connection pads connected to the first redistribution layer;

an encapsulant encapsulating the semiconductor chip in the cavity and covering the first surface of the supporting member; and

a second redistribution layer including an insulating layer having a first surface and a second surface opposing each other, first wiring patterns embedded in the first surface of the insulating layer, second wiring patterns on the second surface of the insulating layer and embedded in the encapsulant, connection vias penetrating through the insulating layer and the encapsulant to connect the wiring structure and at least one of the first wiring patterns and the second wiring patterns to each other, the second surface of the insulating layer being in contact with the encapsulant.

13. A semiconductor package comprising:

a supporting member including a wiring structure connecting an upper surface of the supporting member to a lower surface of the supporting member;

a connection member on the lower surface of the supporting member and including a first redistribution layer connected to the wiring structure;

one or more components in a cavity of the supporting member;

an encapsulant covering the one or more components and the upper surface of the supporting member;

a second redistribution layer including an insulating layer having first and second surfaces opposing each other, the second surface being in contact with the encapsulant, and the second redistribution layer further including an electrode pad embedded in the first surface of the insulating layer and a wiring pattern on the second surface of the insulating layer and embedded in the encapsulant;

a first conductive via penetrating through a first portion of the wiring pattern, extending above the first portion of the wiring pattern, extending below the first portion of the wiring pattern into the encapsulant, and connected to the upper surface of the supporting member,

wherein the first redistribution layer is connected to the electrode pad of the second redistribution layer through the wiring structure of the supporting member, the first conductive via, and the wiring pattern of the second redistribution layer.

14. The semiconductor package of claim 13 , further comprising:

a second conductive via penetrating through a second portion of the wiring pattern, extending below the second portion of the wiring pattern into the encapsulant, connected to the upper surface of the supporting member,

wherein an upper surface of the second conductive via is substantially coplanar with an upper surface of the second portion of the wiring pattern.

15. The semiconductor package of claim 14 , wherein a central portion of the upper surface of the second conductive via is recessed.

16. The semiconductor package of claim 13 , further comprising an interlayer via within the second redistribution layer and connecting a lower portion of the wiring pattern embedded in the encapsulant to an upper portion of the wiring pattern above the lower portion,

wherein an upper width of the interlayer via in contact with the upper portion of the wiring pattern is smaller than a lower width of the interlayer via in contact with the lower portion of the wiring pattern, and

wherein an upper width of the first conductive via above the first portion of the wiring pattern is larger than a lower width of the first conductive via below the first portion of the wiring pattern.