Semiconductor structure including low-K spacer material
View Patent ↗A semiconductor structure includes a substrate, and a replacement metal gate (RMG) structure is attached to the substrate. The RMG structure includes a lower portion and an upper tapered portion. A source junction is disposed on the substrate and attached to a first low-k spacer portion. A drain junction is disposed on the substrate and attached to a second low-k spacer portion. A first oxide layer is disposed on the source junction, and attached to the first low-k spacer portion. A second oxide layer is disposed on the drain junction, and attached to the second low-k spacer portion. A cap layer is disposed on a top surface layer of the RMG structure and attached to the first oxide layer and the second oxide layer.
1. A method comprising:
forming a dummy gate stack on a substrate including a sacrificial spacer on a peripheral of the dummy gate stack;
etching down the sacrificial spacer using an over etch process, wherein the over etch process comprises:
partially recessing the dummy gate stack;
etching the sacrificial spacer down to the partially recessed dummy gate stack; and
etching remaining portions of the sacrificial spacer to form a dummy gate cavity that includes gaps around and above the partially recessed dummy gate stack;
filling a portion of the gaps with low-k spacer material that extends vertically along a sidewall of the dummy gate cavity; and
etching the low-k spacer material on the sidewall of the dummy gate cavity and below the partially recessed dummy gate stack to form a first low-k spacer portion and a second low-k spacer portion disposed above the first low-k spacer portion, wherein the first low-k spacer portion has a corresponding width that is constant as the first low-k spacer portion extends vertically along the sidewall of the dummy gate cavity, and the second low-k spacer portion has a corresponding width that tapers towards the sidewall of the dummy gate cavity as the second low-k spacer portion extends vertically along the sidewall of the dummy gate cavity.
2. The method of claim 1 , further comprising
performing a poly pull process on the partially recessed dummy gate stack;
forming a replacement metal gate (RMG) structure with the first low-k spacer portion and the second low-k spacer portion; and
forming a low-k cap layer over the RMG structure.
3. The method of claim 2 , wherein a height of the low-k cap layer is reduced to an oxide layer of the substrate.
4. The method of claim 2 , wherein the first low-k spacer portion and the second low-k spacer portion each are comprised of a material with a dielectric constant lower than silicon nitride.
5. The method of claim 2 , wherein the low-k cap layer is coupled to the second low-k spacer portion.
6. The method of claim 2 , wherein the low-k cap layer comprises a material with a dielectric constant lower than silicon nitride.
7. The method of claim 2 , wherein the low-k cap layer comprises a same material as the first low-k spacer portion and the second low-k spacer portion.