Package with metal-insulator-metal capacitor and method of manufacturing the same

1. A package comprising:

a chip in a first area of the package;

a molding compound in a second area of the package adjacent to the first area;

a pair of polymer layers stacked on the chip and the molding compound;

a first interconnect structure and a second interconnect structure both between the polymer layers;

a capacitor on the polymer layers and electrically coupled to the first interconnect structure, wherein the capacitor comprises a lower electrode, a dielectric layer overlying the lower electrode, and an upper electrode overlying the dielectric layer, and wherein the dielectric layer extends along a sidewall of the lower electrode;

a conductive structure covering the capacitor and contacting a sidewall of the dielectric layer, wherein the conductive structure comprises a barrier layer and a metal layer, and wherein the metal layer overlies the barrier layer; and

a conductive bump on the polymer layers and electrically coupled to the second interconnect structure, wherein the conductive bump is even with the capacitor.

2. The package according to claim 1 , wherein the dielectric layer wraps around top corners of the lower electrode.

3. The package according to claim 1 , wherein the conductive structure has a sidewall aligned to a first top corner of the upper electrode, wherein the conductive structure wraps a second top corner of the upper electrode, and wherein the first and second top corners are on opposite sides of the upper electrode.

4. The package according to claim 1 , further comprising a third interconnect structure between the polymer layers and laterally spaced from the first interconnect structure, wherein the capacitor overlies the first interconnect structure, and wherein the conductive structure extends continuously from the capacitor to the third interconnect structure.

5. The package according to claim 4 , wherein the lower electrode directly contacts the first interconnect structure, and wherein the conductive structure directly contacts the upper electrode and the third interconnect structure.

6. The package according to claim 1 , wherein the first and second interconnect structures overlie a lower polymer layer of the pair of polymer layers, and wherein the first and second interconnect structures protrude through the lower polymer layer to the chip.

7. The package according to claim 1 , further comprising:

an isolation layer completely covering the capacitor and the conductive structure, wherein the isolation layer defines an opening within which the conductive bump is arranged, and wherein the isolation layer is spaced from the conductive bump.

8. The package according to claim 1 , further comprising:

a second conductive structure contacting a top surface of the second interconnect structure, and further cupping and contacting an underside of the conductive bump.

9. The package according to claim 8 , wherein the second conductive structure comprises a barrier layer and a metal layer, and wherein the metal layer overlies the barrier layer.

10. A package comprising:

a chip in a first area of the package;

a molding compound in a second area of the package adjacent to the first area;

a pair of polymer layers stacked on the chip and the molding compound;

a first interconnect structure and a second interconnect structure both between the polymer layers;

a capacitor on the polymer layers and overlying the first interconnect structure, wherein the capacitor comprises a lower electrode, a dielectric layer overlying the lower electrode, and an upper electrode overlying the dielectric layer, and wherein the dielectric layer extends along a sidewall of the lower electrode;

a conductive layer comprising a first conductive segment overlying the capacitor, and further comprising a second conductive segment overlying the second interconnect structure, wherein the first conductive segment is elevated relative to the second conductive segment and contacts a sidewall of the dielectric layer, and wherein the second conductive segment is even with the capacitor; and

a third interconnect structure between the polymer layers and laterally spaced from the first interconnect structure, wherein the first conductive segment extends continuously from the capacitor to the third interconnect structure.

11. The package according to claim 10 , wherein a top surface of the second conductive segment is between a top surface of the capacitor and a bottom surface of the capacitor.

12. The package according to claim 10 , wherein the dielectric layer contacts the sidewall of the lower electrode and wraps around top corners of the lower electrode.

13. The package according to claim 12 , wherein the first conductive segment wraps around a top corner of the dielectric layer and contacts a sidewall of the dielectric layer.

14. The package according to claim 10 , further comprising:

an isolation layer completely covering the capacitor and the first conductive segment, wherein the isolation layer defines an opening within which the second conductive segment is arranged, and wherein the isolation layer is spaced from the second conductive segment.

15. The package according to claim 10 , wherein the first and second interconnect structures have v-shaped segments protruding through a lower polymer layer of the pair of polymer layers to the chip.

16. A package comprising:

a chip in a first area of the package;

a molding compound in a second area of the package adjacent to the first area;

a pair of polymer layers stacked on the chip and the molding compound;

a first interconnect structure and a second interconnect structure both between the polymer layers;

a capacitor on the polymer layers and overlying the first interconnect structure, wherein the capacitor comprises a lower electrode, a dielectric layer overlying the lower electrode, and an upper electrode overlying the dielectric layer, and wherein the dielectric layer extends along a sidewall of the lower electrode;

a conductive layer comprising a first conductive segment overlying the capacitor, and further comprising a second conductive segment overlying the second interconnect structure, wherein the first conductive segment is elevated relative to the second conductive segment and contacts a sidewall of the dielectric layer, and wherein the first conductive segment has a sidewall aligned to a first top corner of the upper electrode; and

an isolation coating covering the capacitor and the first conductive segment, and further defining an opening exposing the second conductive segment.

17. The package according to claim 16 , wherein a bottom surface of the lower electrode is even with a bottom surface of the second conductive segment.

18. The package according to claim 16 , wherein the first and second interconnect structures respectively contact the capacitor and the second conductive segment, and wherein the first and second interconnect structures protrude through a lower polymer layer of the polymer layers to contact with the chip.

19. The package according to claim 18 , further comprising:

a third interconnect structure vertically between the polymer layers, and laterally between the first and second interconnect structures, wherein the first conductive segment extends continuously from contact with a top surface of the upper electrode to contact with a top surface of the third interconnect structure, and wherein the third interconnect structure protrudes through the lower polymer layer to contact with the chip.

20. The package according to claim 16 , wherein the first conductive segment wraps around a second top corner of the upper electrode, and wherein the first and second top corners are on opposite sides of the upper electrode.