Semiconductor device, interconnection structure and method for forming the same
A semiconductor device is provided. The semiconductor device includes a source/drain region, a silicide layer on the source/drain region, an interlayer dielectric (ILD) layer over the silicide layer, and a source drain contact. The source/drain contact has a top portion extending through the ILD layer and a bottom portion embedded in the silicide layer.
1. A semiconductor device, comprising:
a source/drain region on a semiconductor substrate;
a silicide layer on the source/drain region;
an interlayer dielectric (ILD) layer over the silicide layer; and
a source/drain contact having a top portion extending through the ILD layer and a bottom portion embedded in the silicide layer, wherein the bottom portion of the source/drain contact has a slanted sidewall and a curved sidewall extending downwardly from the slanted sidewall and being more curved than the slanted sidewall.
2. The semiconductor device of claim 1 , wherein the bottom portion of the source/drain contact has a first segment and a second segment below the first segment, and the first segment and the second segment have different outer profiles.
3. The semiconductor device of claim 2 , wherein the first segment of the bottom portion and the top portion have different outer profiles.
4. The semiconductor device of claim 3 , wherein a sidewall of the first segment of the bottom portion has a slope lower than a sidewall of the top portion.
5. The semiconductor device of claim 3 , wherein the outer profile of the second segment is rounded.
6. The semiconductor device of claim 1 , wherein the bottom portion of the source/drain contact has a pointed tip.
7. The semiconductor device of claim 1 , wherein the bottom portion of the silicide layer has a convex surface.
8. An interconnection structure, comprising:
a first interlayer dielectric (ILD) layer;
a metal line embedded in the first ILD layer;
a second ILD layer over the metal line; and
a metal via having a top portion extending through the second ILD layer and a bottom portion embedded in the metal line, wherein the bottom portion of the metal via has a rounded end and sloped sidewalls extending upwardly from the rounded end, the sloped sidewalls being straighter than the rounded end.
9. The interconnection structure of claim 8 , wherein the top portion and the bottom portion have different outer profiles.
10. The interconnection structure of claim 8 , wherein the bottom portion has a first segment and a second segment below the first segment, and the first segment and the second segment have different outer profiles.
11. The interconnection structure of claim 10 , wherein a width of the first segment is greater than a maximal width of the second segment.
12. The interconnection structure of claim 8 , wherein a width of the top portion is greater than a maximal width of the bottom portion.
13. The interconnection structure of claim 8 , wherein the bottom portion of the metal via has a cross-sectional profile in a shape of triangle, trapezoid, or arc.
14. A method, comprising:
forming a silicide layer over an epitaxy structure;
forming a dielectric layer over the silicide layer;
etching the dielectric layer and the silicide layer to form a recess through the dielectric layer and in the silicide layer, wherein the etching the dielectric layer and the silicide layer is performed such that the recess has a bottom portion in the silicide layer, the bottom portion has a first sidewall and a second sidewall extending below the first sidewall, and the first sidewall and the second sidewall form an angle;
laterally expanding a first portion of the recess through the dielectric layer after forming the recess; and
forming a conductive feature in the recess.
15. The method of claim 14 , wherein laterally expanding the dielectric layer comprises rounding a top corner of the recess.
16. The method of claim 14 , wherein etching the silicide layer is performed such that a portion of the recess in the silicide layer tapers downwardly.
17. The method of claim 14 , wherein etching the silicide layer is performed such that the recess has a rounded bottom surface.
18. The method of claim 14 , wherein the first sidewall and the second sidewall have different outer profiles.
19. The method of claim 14 , wherein the first sidewall and the second sidewall have different slopes.
20. The method of claim 19 , wherein the first sidewall is straighter than the second sidewall.