Maximum voltage selection circuit

1. A voltage selection circuit, comprising:

a power detection circuit configured to compare an output voltage with a first input voltage and a second input voltage, respectively;

a latch circuit, coupled to the power detection circuit, and configured to flip respective logic states of a pair of output signals when the output voltage is lower than either the first input voltage or the second input voltage; and

a selection circuit, coupled to the latch circuit, and configured to use either the first input voltage or the second input voltage as the output voltage based on the respective logic states of the pair of output signals, wherein the power detection circuit comprises:

a first transistor gated by the first input voltage and sourced from the second input voltage;

a second transistor gated by the second input voltage and sourced from the first input voltage;

a third transistor gated by the output voltage and sourced from the first input voltage; and

a fourth transistor gated by the output voltage and sourced from the second input voltage.

2. The circuit of claim 1 , wherein each of the first, second, third, and fourth transistors comprises a p-type metal-oxide-semiconductor field-effect-transistor (PMOSFET).

3. The circuit of claim 1 , wherein when the output voltage is equal to one of the first and second input voltages and lower than the other of the first and second input voltages, either currents flowing through the second and third transistors or currents flowing through the first and fourth transistors increase.

4. The circuit of claim 3 , wherein the currents flowing through the second and third transistors and the currents flowing through the first and fourth transistors are each a sub-threshold current.

5. The circuit of claim 3 , wherein when either the currents flowing through the second and third transistors or the currents flowing through the first and fourth transistors increase, the latch circuit flips the respective logic states of the pair of output signals.

6. The circuit of claim 1 , wherein the selection circuit further comprises:

a first switch configured to couple the first input voltage to the output voltage in response to the logic state of one of the pair of output signals; and

a second switch configured to couple the second input voltage to the output voltage in response to the logic state of the other of the pair of output signals.

7. The circuit of claim 1 , wherein the selection circuit further comprises:

an SR latch circuit configured to receive the respective logic states of the pair of output signals of the latch circuit as inputs.

8. A voltage selection circuit configured to select a maximum voltage from at least a first input voltage and a second input voltage as an output voltage, comprising:

a power detection circuit that comprises:

a first transistor that is gated by the first input voltage and sourced from the second input voltage; a second transistor gated by the second input voltage and sourced from the first input voltage; a third transistor gated by the output voltage and sourced from the first input voltage; and a fourth transistor gated by the output voltage and sourced from the second input voltage; and

a latch circuit, coupled to the power detection circuit, and configured to flip respective logic states of a pair of output signals when the output voltage is lower than either the first input voltage or the second input voltage.

9. The circuit of claim 8 , wherein each of the first, second, third, and fourth transistors comprises a p-type metal-oxide-semiconductor field-effect-transistor (PMOSFET).

10. The circuit of claim 8 , further comprising:

a selection circuit, coupled to the latch circuit, and configured to use either the first input voltage or the second input voltage as the output voltage based on the respective logic states of the pair of output signals.

11. The circuit of claim 10 , wherein the selection circuit further comprises:

a first switch configured to couple the first input voltage to the output voltage in response to the logic state of one of the pair of output signals; and

a second switch configured to couple the second input voltage to the output voltage in response to the logic state of the other of the pair of output signals.

12. The circuit of claim 10 , wherein the selection circuit further comprises:

an SR latch circuit configured to receive the respective logic states of the pair of output signals of the latch circuit as inputs.

13. The circuit of claim 8 , wherein when the output voltage is equal to one of the first and second input voltages and lower than the other of the first and second input voltages, either currents flowing through the second and third transistors or currents flowing through the first and fourth transistors increase.

14. The circuit of claim 13 , wherein the currents flowing through the second and third transistors and the currents flowing through the first and fourth transistors are each a sub-threshold current.

15. The circuit of claim 13 , wherein when either the currents flowing through the second and third transistors or the currents flowing through the first and fourth transistors increase, the latch circuit flips the respective logic states of the pair of output signals.

16. A method, comprising:

providing an output voltage of a voltage selection circuit that is selected to follow one of a first input voltage and a second input voltage of the voltage selection circuit;

using a plurality of transistors that each operates under a sub-threshold mode to monitor whether the output voltage drops below the other of the first and second input voltages; and

when the output voltage drops below the other of the first and second input voltages, flipping respective logic states of output signals of a latch circuit so as to cause the output voltage to follow the other of the first and second input voltages, wherein the plurality of transistors comprise:

first transistor gated by the first input voltage and sourced from the second input voltage;

a second transistor gated by the second input voltage and sourced from the first input voltage;

a third transistor gated by the output voltage and sourced from the first input voltage; and

a fourth transistor gated by the output voltage and sourced from the second input voltage.

17. The method of claim 16 , wherein each of the first, second, third, and fourth transistors comprises a p-type metal-oxide-semiconductor field-effect-transistor (PMOSFET).