Capacitor die embedded in package substrate for providing capacitance to surface mounted die
A package substrate is disclosed. The package substrate includes a die package in the package substrate located at least partially underneath a location of a power delivery interface in a die that is coupled to the surface of the package substrate. Connection terminals are accessible on a surface of the die package to provide connection to the die that is coupled to the surface of the package substrate. Metal-insulator-metal layers inside the die package are coupled to the connection terminals.
1. A package substrate, comprising:
a capacitor die embedded in the package substrate at least partially underneath a surface mounted die, wherein the capacitor die is a single-sided MIM capacitor die;
connection terminals accessible at a surface of the capacitor die embedded in the package substrate to provide connection to the surface mounted die, the surface of the capacitor die facing the surface mounted die; and
metal-insulator-metal layers inside the capacitor die embedded in the package substrate coupled to the connection terminals.
2. The package substrate of claim 1 , wherein the surface mount die comprises an integrated circuit die, an FPGA or an ASIC.
3. The package substrate of claim 1 , wherein the capacitor die is in front side build-up layers of the package substrate.
4. The package substrate of claim 1 , wherein the capacitor die includes a vertical wiring path to the surface mounted die.
5. The package substrate of claim 1 , wherein the capacitor die supports at least two power domains.
6. The package substrate of claim 1 , wherein the capacitor die occupies two or less levels of the package substrate.
7. The package substrate of claim 1 , wherein the capacitor die is in a core of the package substrate.
8. The package substrate of claim 1 , wherein the surface mounted die is surrounded by other surface mounted die that are coupled to the surface mounted die by EMIB connectors.
9. A package substrate, comprising:
package interconnects;
dielectric layers;
metal layers; and
an embedded capacitor die in the package substrate that is at least partially underneath a surface mounted die, wherein the embedded capacitor die is a single-sided MIM capacitor die.
10. The package substrate of claim 9 , wherein the surface mount die comprises an integrated circuit die, an FPGA or an ASIC.
11. The package substrate of claim 9 , wherein the embedded capacitor die is in front side build-up layers of the package substrate.
12. The package substrate of claim 9 , wherein the embedded capacitor die includes a vertical path to the surface mounted die.
13. The package substrate of claim 9 , wherein the embedded capacitor die supports at least two power domains.
14. The package substrate of claim 9 , wherein the embedded capacitor die occupies two or less levels of the package substrate.
15. The package substrate of claim 9 , wherein the surface mounted die is surrounded by other surface mounted die that are coupled to the surface mounted die by EMIB connectors.
16. A method, comprising:
identifying a space in a package substrate of a surface mount die;
embedding a capacitor die in the space of the package substrate in build-up layers of the space, wherein the capacitor die is a single-sided MIM capacitor die; and
connecting the surface mount die to the capacitor die with a connector.
17. The method of claim 16 , wherein the capacitor die is embedded in front side build-up layers of the package substrate.
18. The method of claim 16 , wherein the connector provides a vertical path between the capacitor die and the surface mount die.
19. The method of claim 16 , wherein the capacitor die supports at least two power domains.
20. The method of claim 16 , wherein the capacitor die occupies two or less levels of the package substrate.