IP Library Granted Patent US 10,332,981
Granted Patent B1
US 10,332,981 · App. 15/943,657 · Granted Jun 25, 2019

Semiconductor device and method for fabricating the same

Inventors: Yu-Ying Lin (Tainan, TW); Yi-Liang Ye (Kaohsiung, TW); Sung-Yuan Tsai (Yunlin County, TW); Chun-Wei Yu (Tainan, TW); Yu-Ren Wang (Tainan, TW); Zhen Wu (Kaohsiung, TW); Tai-Yen Lin (Changhua County, TW)
Assignee: UNITED MICROELECTRONICS CORP.
H01L29/66636H01L21/26506H01L21/28587H01L21/3065H01L21/30604H01L21/76843H01L21/76855H01L29/0847H01L29/7848H01L21/02631H01L21/2855H01L21/28518
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 10,332,981
App. No.
15/943,657
Granted
Jun 25, 2019
Kind
B1
Abstract

A method for fabricating semiconductor device includes the steps of: forming a first gate structure on a substrate; performing a first etching process to form a recess adjacent to the first gate structure; performing an ion implantation process to form an amorphous layer directly under the recess; performing a second etching process to remove the amorphous layer; and forming an epitaxial layer in the recess.

Claims (10)

1. A semiconductor device, comprising:

a first gate structure on a substrate;

an epitaxial layer adjacent to the first gate structure; and

a bump on the substrate adjacent to the first gate structure and directly under the epitaxial layer.

2. The semiconductor device of claim 1 , wherein a top surface of the bump comprises a planar surface.

3. The semiconductor device of claim 1 , wherein the bump comprises two inclined sidewalls.

4. The semiconductor device of claim 3 , further comprising a second gate structure on the substrate, wherein the bump is between the first gate structure and the second gate structure.

5. The semiconductor device of claim 4 , wherein the epitaxial layer comprises a first V-shape under the first gate structure and a second V-shape under the second gate structure.

6. The semiconductor device of claim 5 , wherein the first V-shape and the second V-shape are connected to the two inclined sidewalls directly.

7. The semiconductor device of claim 1 , wherein the bump and the substrate comprise same material.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 26, 2021
From: UNITED MICROELECTRONICS CORPORATION
To: MARLIN SEMICONDUCTOR LIMITED
Reel/Frame 056991/0292 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 2, 2018
From: LIN, YU-YING; YE, YI-LIANG; TSAI, SUNG-YUAN; YU, CHUN-WEI; WANG, YU-REN; WU, ZHEN; LIN, TAI-YEN
To: UNITED MICROELECTRONICS CORP.
Reel/Frame 045419/0911 →
Priority Claims (1)
CN 2018 1 0188894 · Mar 8, 2018 · national
Cited By (1)
US 12,237,404