Semiconductor device and fabrication method thereof

1. A fabrication method of a semiconductor device, comprising:

providing a base substrate;

forming gate structures on the base substrate;

forming source/drain doped regions in the base substrate on sides of each gate structure, wherein the source/drain doped regions have recessed top surfaces and are doped with source/drain ions;

doping into the recessed top surfaces of the source/drain doped regions with contact ions to form contact doped regions in top portions of the source/drain doped regions, wherein the contact ions have a conductivity type same as the source/drain ions; and

forming first compensating doped regions in the base substrate under the source/drain doped regions and adjacent to the source/drain doped regions, wherein

the first compensating doped regions include first compensating layers, in the base substrate under the source/drain doped regions, and second compensating layers, in the base substrate between the first compensating layers and the source/drain doped regions.

2. The fabrication method according to claim 1 , wherein:

doping into the recessed top surfaces of the source/drain doped regions with contact ions includes a contact ion implantation process, using an implanting energy of about 2 keV to about 5 keV, an implanting dose of about 1E14 atom/cm 2 to about 2E15 atom/cm 2 ; and an implanting angle of about 0 degree to about 15 degrees between an implanting direction and normal direction of the base substrate.

3. The fabrication method according to claim 1 , wherein a concentration of the contact ions in the contact doped regions is about 40% to 80% of a concentration of the source/drain ions in the source/drain doped regions.

4. The fabrication method according to claim 1 , wherein the contact ions are N-type when the semiconductor device is N-type and the contact ions are P-type when the semiconductor device is P-type.

5. The fabrication method according to claim 1 , wherein:

when the semiconductor device is a planar metal-oxide-semiconductor transistor, forming the source/drain doped region includes:

forming an initial source/drain doped region with the source/drain ions in the base substrate on each side of the gate structure, wherein the initial source/drain doped region includes a central region and a marginal region surrounding the central region and the central region has a top surface coplanar with the marginal region; and

etching the initial source/drain doped region to form the source/drain doped region, wherein an etching depth of the central region is deeper than an etching depth of the marginal region; and

when the semiconductor device is a fin field effect transistor, forming the source/drain doped region includes:

forming an initial source/drain doped region with the source/drain ions in the base substrate on each side of the gate structure, wherein the initial source/drain doped region includes a first region and a second region on two sides of the first region, and a direction from the second region to the first region is perpendicular to an extending direction of the gate structure, and the first region and the second region have a coplanar top suface; and

etching the initial source/drain doped region to form the source/drain doped region, wherein an etching depth of the first regions is deeper than an etching depth of the second regions.

6. The fabrication method according to claim 5 , wherein:

the initial source/drain doped region is etched by a dry etching process using:

gases including a etching gas and a diluting gas, the etching gas including a carbon-hydrogen-fluorine based gas, a carbon-fluorine based gas, or a combination thereof, the diluting gas including Ar, O 2 , N 2 , C O2 , COS, or a combination thereof;

a flow rate of the etching gas of about 10 sccm to about 100 sccm;

a flow rate of the diluting gas of about 0 sccm to about 500 sccm;

a source RF power of about 100 W to about 500 W;

a bias RF power of bout 10 W to 50 w; and

a chamber pressure of about 4 mtorr to about 100 mtorr.

7. The fabrication method according to claim 5 ,

wherein the first compensating doped regions have first compensating ions having a conductivity type same as the source/drain ions and having a concentration less than the concentration of the source/drain ions in the source/drain doped regions; and

wherein the first compensating doped regions are formed by: before etching the initial source/drain doped regions, doping the base substrate under the initial source/drain doped regions with the first compensating ions, to form the first compensating doped regions in the base substrate under the source/drain doped regions and adjacent to the source/drain doped regions.

8. The fabrication method according to claim 7 , wherein:

the first compensating layers have first compensating ions with a first concentration less than the concentration of the source/drain ions in the source/drain doped regions;

the second compensating layers have second compensating ions with a second concentration greater than the first concentration and less than the concentration of the source/drain ions in the source/drain doped regions; and

the first compenasting, doped regions are formed by:

doping the base substrate under the initial source/drain doped regions with the first compensating ions to form the first compensating layers with the first concentration less than the concentration of the source/drain ions in the source/drain doped regions, having a portion of the base substrate between the first compensating layers and the initial source/drain doped regions; and

doping a portion of the base substrate between the first compensating layers and the initial source/drain doped regions with the first compensating ions to form the second compensating layers with the second concentration greater than the first concentration and smaller than the concentration of the source/drain ions in the source/drain doped regions.

9. The fabrication method according to claim 8 , wherein:

the second concentration is about 30% to 70% of the concentration of the source/drain ions in the source/drain doped regions, and

the first concentration is about 30% to 70% of the second concentration.

10. The fabrication method according to claim 9 , wherein:

the first compensating layers are formed by a first ion implantation process using an implanting energy of about 10 keV to about 50 keV, an implanting dose of about 1E13 atom/ cm 2 to about 6E14 atom/ cm 2 , and an implanting angle of about 0 degree to about 15 degrees; and

the second compensating layers are formed by a second ion implantation process using an implanting energy of about 6 keV to about 11 keV, an implanting dose of about 1E15 atom/ cm 2 to about 5E15 atom/ cm 2 , and an implanting angle of about 0 degrees to about 15 degrees between an implanting direction and normal direction of the base substrate.

11. The fabrication method according to claim 5 , further including:

forming second compensating doped regions in the source/drain doped regions under the contact doped regions by doping a portion of the initial source/drain doped regions with second compensating ions before etching the initial source/drain doped regions,

wherein the second compensating ions have a conductivity type same as the source/drain ions and have a concentration less than the concentration of the contact ions in the contact doped regions.

12. The fabrication method according to claim 11 , wherein a concentration of the second compensating ions is about 50% to about 70% of a concentration of the contact ions in the contact doped regions.

13. The fabrication method according to claim 11 ; wherein:

the second compensating doped regions are formed by a third ion implantation process using an implanting energy is of about 4 keV to about 6 keV, an implanting dose of about 0.5E14 atom/ cm 2 to about 1.5E15 atom/ cm 2 , and an implanting angle of about 0 degree to about 15 degrees between an implanting direction and normal direction of the base substrate.

14. A semiconductor device, comprising:

a base substrate;

a gate structure on the base substrate;

source/drain doped regions in the base substrate on sides of the gate structure, wherein the source/drain doped regions have recessed top surfaces and are doped with source/drain ions; and

contact doped regions in the top portions of the source/drain doped region, with contact ions having a conductivity type same as the source/drain ions, wherein the recessed top surfaces of the source/drain doped regions are surfaces of the contact doped regions; and

first compensating doped regions in the base substrate under the source/drain doped, regions and adjacent to the source/drain doped regions, wherein:

the first compensating doped regions include first compensating lavers, in the base substrate under the source/drain doped regions, and second compensating layers, in the base substrate between the first compensating layers and the source/drain doped regions.

15. The semiconductor device according to claim 14 , wherein a concentration of the contact ions in the contact doped regions is about 40% to about 80% of a concentration of the source/drain ions in the source/drain doped regions.

16. The semiconductor device according to claim 14 , wherein the first compensating doped regions have first compensating ions which have a conductivity type same as the source/drain ions and have a concentration less than the concentration of the source/drain ions in the source/drain doped regions.

17. The semiconductor device according to claim 14 , further including second compensating doped regions in the source/drain doped regions under the contact doped regions, wherein the second compensating doped regions have second compensating ions which have a conductivity type same as the source/drain ions and have a concentration less than the concentration of the contact ions in the contact doped regions.

18. The semiconductor device according to claim 17 , wherein the concentration of the second compensating ions in the second compensating doped regions is about 50% to about 70% of the concentration of the contact ions in the contact doped regions.

19. A semiconductor device, comprising:

a base substrate;

a gate structure on the base substrate;

source/drain doped regions in the base substrate on sides of the gate structure, wherein the source/drain doped regions have recessed top surfaces and are doped with source/drain ions;

contact doped regions in the top portions of the source/drain doped region, with contact ions having a conductivity type same as the source/drain ions, wherein the recessed top surfaces of the source/drain doped regions are surfaces of the contact doped regions; and

first compensating doped regions in the base substrate under the source/drain doped regions and adjacent to the source/drain doped regions, wherein the first compensating doped regions have first compensating ions which have a conductivity type same as the source/drain ions and have a concentration less than the concentration of the source/drain ions in the source/drain doped regions, wherein:

the first compensating doped regions include first compensating layers in the base substrate under the source/drain doped regions, and second compensating layers in the base substrate between the first compensating layers and the source/drain doped regions; and

the first compensating layers have first compensating ions with a first concentration less than the concentration of the source/drain ions in the source/drain doped regions; and

the second compensating layers have second compensating ions with a second concentration greater than the first concentration but less than the concentration of the source/drain ions in the source/drain doped regions.

20. The semiconductor device according to claim 19 , wherein the second concentration is about 30% to 70% of the concentration of the source/drain ions in the source/drain doped regions, and the first concentration is about 30% to 70% of the second concentration.