Time-based delay line analog to digital converter
A differential digital delay line analog-to-digital converter (ADC) includes differential digital delay lines, a circuit including a set of delay elements included in the differential digital delay lines, and another circuit including another set of delay elements included in the differential digital delay lines. The first circuit is configured to generate data representing an analog to digital conversion of an input. The second circuit is configured to calibrate a source to the differential digital delay lines.
1. A differential digital delay line analog-to-digital converter (ADC), comprising:
a plurality of differential digital delay lines;
a first circuit comprising a set of delay elements included in the differential digital delay lines; and
a second circuit comprising another set of delay elements included in the differential digital delay lines; wherein:
the first circuit is configured to generate data representing an analog to digital conversion of an input; and
the second circuit is configured to calibrate a source to the differential digital delay lines based on an out of input range determination.
2. The ADC of claim 1 , wherein the first circuit is configured to measure a difference between an input voltage and a reference voltage.
3. The ADC of claim 1 , further comprising a current source circuit configured to mirror reference currents to each of the differential digital delay lines.
4. The ADC of claim 1 , further comprising a current source circuit configured to mirror reference currents to each of the differential digital delay lines, wherein the second circuit is configured to adjust the reference currents to minimize error.
5. The ADC of claim 1 , further comprising a transconductor configured to convert an input differential voltage to a differential current, wherein the first circuit is configured to measure the differential current and generate data representing the differential voltage.
6. The ADC of claim 1 , further comprising a transconductor configured to:
convert an input differential voltage to a differential current; and
accept an input based on the plurality of differential digital delay lines to adjust a voltage-to-current range.
7. The ADC of claim 1 , wherein each differential digital delay line includes a chain of current limited buffers.
8. The ADC of claim 1 , wherein:
a given differential digital delay line is configured to operate at a speed according to a differential current applied to the given differential digital delay line;
the ADC further comprises a latch; and
the latch is configured to save data from a slower differential digital delay line upon a completion of faster differential digital delay line.
9. The ADC of claim 1 , further comprising a third circuit comprising yet another set of delay elements included in the differential digital delay line, wherein the third circuit is configured to produce data to indicate a degree to which an input to the ADC is out of an input range.
10. The ADC of claim 1 , further comprising a third circuit the calibrate the ADC by adjusting lengths of the digital delay lines independently from one another.
11. A differential digital delay line analog-to-digital converter (ADC), comprising:
a plurality of differential digital delay lines;
a first circuit comprising a set of delay elements included in the differential digital delay lines; and
a second circuit comprising another set of delay elements included in the differential digital delay lines; wherein:
the first circuit is configured to generate data representing an analog to digital conversion of an input; and
the second circuit is configured to produce data to indicate a degree to which an input to the ADC is out of an input range.
12. The ADC of claim 11 , wherein the first circuit is configured to measure a difference between an input voltage and a reference voltage.
13. The ADC of claim 11 , further comprising a current source circuit configured to mirror reference currents to each of the differential digital delay lines.
14. The ADC of claim 11 , further comprising a current source circuit configured to mirror reference currents to each of the differential digital delay lines, wherein the second circuit is configured to adjust the reference currents to minimize error.
15. The ADC of claim 11 , further comprising a transconductor configured to convert an input differential voltage to a differential current, wherein the first circuit is configured to measure the differential current and generate data representing the differential voltage.
16. The ADC of claim 11 , further comprising a transconductor configured to:
convert an input differential voltage to a differential current; and
accept an input based on the plurality of differential digital delay lines to adjust a voltage-to-current range.
17. The ADC of claim 11 , wherein each differential digital delay line includes a chain of current limited buffers.
18. The ADC of claim 11 , wherein:
a given differential digital delay line is configured to operate at a speed according to a differential current applied to the given differential digital delay line;
the ADC further comprises a latch; and
the latch is configured to save data from a slower differential digital delay line upon a completion of faster differential digital delay line.
19. The ADC of claim 11 , further comprising a third circuit comprising a yet another set of delay elements included in the differential digital delay line, wherein the third circuit is configured to calibrate a source to the differential digital delay lines.
20. The ADC of claim 10 , The ADC of claim 11 , further comprising a third circuit the calibrate the ADC by adjusting lengths of the digital delay lines independently from one another.
21. A differential digital delay line analog-to-digital converter (ADC), comprising:
a plurality of differential digital delay lines;
a first circuit comprising a set of delay elements included in the differential digital delay lines; and
a transconductor configured to:
convert an input differential voltage to a differential current; and
accept an input based on the plurality of differential digital delay lines to adjust a voltage-to-current range.
22. The ADC of claim 21 , further comprising a second circuit comprising a yet another set of delay elements included in the differential digital delay line, wherein the second circuit is configured to produce data to indicate a degree to which an input to the ADC is out of an input range.