IP Library Granted Patent US 10,770,237
Granted Patent B2
US 10,770,237 · App. 15/954,140 · Granted Sep 8, 2020

Multilayer electronic component

Inventors: Soo Hwan Son (Suwon-Si, KR); Jae Yeol Choi (Suwon-si, KR); Young Ghyu Ahn (Suwon-si, KR)
Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
H01G4/385H01G4/232H01G4/30H01G4/1227
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Quick Facts
Patent No.
US 10,770,237
App. No.
15/954,140
Granted
Sep 8, 2020
Kind
B2
Abstract

A multilayer electronic component includes: a laminate having a plurality of multilayer capacitors are disposed to be adjacent to each other, each of the multilayer capacitors including a body including dielectric layers and first and second internal electrodes alternately exposed through two end surfaces of the body facing each other in a length direction with each of the dielectric layers interposed therebetween, and first and second external electrodes disposed on the two end surfaces of the body in the length direction, respectively; and first and second terminals disposed on the laminate to cover a plurality of first and second external electrodes, respectively.

Claims (19)

1. A multilayer electronic component comprising:

a laminate having a plurality of multilayer capacitors disposed to be adjacent to each other, each of the plurality of multilayer capacitors including a body including dielectric layers and first and second internal electrodes alternately exposed through two end surfaces of the body facing each other in a length direction with each of the dielectric layers interposed therebetween in a thickness direction, and first and second external electrodes disposed on the two end surfaces of the body in the length direction, respectively; and

first and second terminals disposed on the laminate to cover a plurality of first and second external electrodes, respectively,

wherein the first and second terminals respectively include first and second connection portions disposed on two end surfaces of the laminate in the length direction, and first and second band portions extending from circumferential edges of the first and second connection portions to cover at least a portion of top and bottom surfaces of the laminate in the thickness direction,

wherein circumferential edges of the first and second external electrodes are arranged within circumferential edges of the two end surfaces of the body in the thickness direction, respectively, and

wherein a surface of a multilayer capacitor of the plurality of multilayer capacitors directly contacts a surface of an adjacent multilayer capacitor of the plurality of multilayer capacitors.

2. The multilayer electronic component of claim 1 , wherein the laminate includes the plurality of multilayer capacitors arranged in parallel in a horizontal direction.

3. The multilayer electronic component of claim 1 , wherein the laminate includes the plurality of multilayer capacitors stacked in the thickness direction.

4. The multilayer electronic component of claim 3 , wherein a first multilayer capacitor disposed on a lowermost layer of the laminate has a lower capacitance than a second multilayer capacitor disposed on an upper side of the laminate.

5. The multilayer electronic component of claim 3 , wherein a first body of a first multilayer capacitor disposed on a lowermost layer of the laminate is formed of a material having a dielectric constant smaller than that of a second body of a second multilayer capacitor disposed on an upper side of the laminate.

6. The multilayer electronic component of claim 3 , wherein a first body of a first multilayer capacitor disposed on a lowermost layer of the laminate is configured so that the number of stacked internal electrodes in the first body is smaller than that of a second body of a second multilayer capacitor disposed on an upper side of the laminate.

7. The multilayer electronic component of claim 3 , wherein 30×t≤C1≤100×t in which t is a thickness of each of the dielectric layers, and C1 is the sum of thicknesses of two adjacent cover regions of two adjacent multilayer capacitors of the laminate, wherein each of the two adjacent multilayer capacitors includes two cover regions respectively disposed on upper and lower sides thereof.

8. The multilayer electronic component of claim 1 , wherein each of the first and second band portions covers a portion of front and rear surfaces of the laminate in a width direction.

9. The multilayer electronic component of claim 1 , wherein the laminate includes the plurality of multilayer capacitors arranged in parallel in a horizontal direction and stacked in a vertical direction at the same time.

10. The multilayer electronic component of claim 9 , wherein a first multilayer capacitor disposed on a lowermost layer of the laminate has a lower capacitance than a second multilayer capacitor disposed on an upper side of the laminate.

11. The multilayer electronic component of claim 9 , wherein a first body of a first multilayer capacitor disposed on a lowermost layer of the laminate is formed of a material having a dielectric constant smaller than that of a second body of a second multilayer capacitor disposed on an upper side of the laminate.

12. The multilayer electronic component of claim 9 , wherein a first body of a first multilayer capacitor disposed on a lowermost layer of the laminate is configured so that the number of stacked internal electrodes in the first body is smaller than that of a second body of a second multilayer capacitor disposed on an upper side of the laminate.

13. The multilayer electronic component of claim 9 , wherein 30×t≤C1≤100×t in which t is a thickness of each of the dielectric layers, and C1 is the sum of thicknesses of two adjacent cover regions of two adjacent multilayer capacitors of the laminate, wherein each of the two adjacent multilayer capacitors includes two cover regions respectively disposed on upper and lower sides thereof.

14. The multilayer electronic component of claim 1 , wherein the bodies of the multilayer capacitor and the adjacent multilayer capacitor of the plurality of multilayer capacitors are discrete.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 16, 2018
From: SON, SOO HWAN; CHOI, JAE YEOL; AHN, YOUNG GHYU
To: SAMSUNG ELECTRO-MECHANICS CO., LTD.
Reel/Frame 045554/0423 →
Priority Claims (1)
KR 10-2017-0177465 · Dec 21, 2017 · national
Continuity (1)
Related Publication 20190198252A1 · Jun 27, 2019
Cited By (1)
US 12,374,496