Non-volatile memory with fast partial page operation
A non-volatile memory system comprises a memory structure and a control circuit connected to the memory structure. The memory structure includes one or more planes of non-volatile memory cells. Each plane is divided into a plurality of partial planes. The control circuit is configured to write to and read from the memory cells by writing a partial page into a particular partial plane and reading the partial page from the particular partial plane using a set of parameters optimized for the particular partial plane.
1. An apparatus, comprising:
a word line;
a plurality of non-volatile memory cells connected along the word line;
a word line driver configured to bias the word line; and
a control circuit connected to the word line driver and configured to perform a memory operation on a selected subset the of memory cells by biasing the word line based on a location of the selected subset of memory cells along the word line.
2. The apparatus of claim 1 ,
a plurality of bit lines, each of the memory cells connected to a corresponding one of the bit lines; and
a decoding circuit connected to the bit lines and configured to select the selected subset of memory cells from a plurality of non-interleaved subsets of the memory cells.
3. The apparatus of claim 2 , wherein each of the non-interleaved subsets of the memory cells includes one or more redundant memory cells.
4. The apparatus of claim 1 wherein:
the word line driver is configured to bias the word line by applying one of a plurality of program voltage pulse levels, wherein an amplitude of a voltage pulse applied to the word line when writing data to a selected subset of the memory cells is dependent on the location on the selected subset of memory cells along the word line.
5. The apparatus of claim 4 , wherein the control circuit is configured to store data in the memory cells in a binary format and write data to the selected subset of memory cells by applying a single voltage pulse to the word line.
6. The apparatus of claim 4 , wherein the word line driver is configured to apply a program voltage pulse having a larger amplitude for a subset of the memory cells further from the word line driver than for a subset of the memory cells nearer the word line driver.
7. The apparatus of claim 1 , wherein:
the word line driver is configured to bias the word line by applying one of a plurality of sensing waveforms to the word line, wherein an amplitude of a sensing waveform applied to the word line when reading data from the selected subset of the memory cells is dependent on the location on the selected subset of memory cells along the word line.
8. The apparatus of claim 7 , wherein the word line driver is configured to apply a sensing waveform having a larger amplitude for a subset of the memory cells further from the word line driver than for a subset of the memory cells nearer the word line driver.
9. The apparatus of claim 1 , wherein:
the control circuit is configured to receive a partial page of data, break the partial page of data into a plurality of chunks of data, scramble the chunks of data, and write the scrambled plurality of chunks of data to the selected subset of the memory cells.
10. The apparatus of claim 1 , wherein the memory cells comprise a memory array of a monolithic three-dimensional semiconductor memory device in which the memory cells are arranged in multiple physical levels above a silicon substrate and comprise a charge storage medium.
11. The apparatus of claim 1 , each of the memory cells comprising a phase change memory material.
12. The apparatus of claim 4 , wherein the selected subset of memory cells is one of a plurality of contiguous non-overlapping subsets of the memory cells connected along the word line.
13. The apparatus of claim 12 , wherein the apparatus further comprises:
a plurality of bit lines, each of the memory cells connects along a corresponding one of the bit lines, and
wherein the control circuit is connected to the bit lines and is further configured to bias bit lines corresponding to the memory cells of the selected subset to a program enable voltage and bias bit lines corresponding to the memory cells of subsets other than the selected subset to a program inhibit voltage when writing data to the selected subset of the memory cells.
14. The apparatus of claim 13 , wherein the control circuit is configured to store data in the memory cells in a binary format and write data to the selected subset of memory cells by applying a single voltage pulse to the word line.
15. The apparatus of claim 14 , wherein the control circuit is further configured to:
subsequent to writing data to the selected subset of memory cells, write data to a second subset of memory cells by applying a single voltage pulse to the word line while biasing the bit lines corresponding to the memory cells of the selected subset to the program inhibit voltage and biasing bit lines corresponding to the memory cells of the second subset to a program enable voltage.
16. The apparatus of claim 4 , wherein the control circuit is configured to store data in the memory cells in a multi-level cell format and write data to the selected subset of memory cells by applying a sequence of voltage pulses to the word line.
17. The apparatus of claim 16 , wherein an amplitude of an initial voltage pulse of the sequence of voltage pulses applied to the word line when writing data to a selected subset of the memory cells is dependent on the location on the selected subset of memory cells along the word line.
18. The apparatus of claim 4 , wherein the control circuit is further configured to bias the word line by applying one of a plurality of sensing waveforms to the word line, wherein an amplitude of a sensing waveform applied to the word line when reading data from the selected subset of the memory cells is dependent on the location on the selected subset of memory cells along the word line.
19. The apparatus of claim 1 , wherein:
the word line driver is configured to bias the word line by applying one of a plurality of program voltage pulse levels, wherein a duration of a voltage pulse applied to the word line when writing data to a selected subset of the memory cells is dependent on the location on the selected subset of memory cells along the word line.
20. The apparatus of claim 19 , wherein the control circuit is configured to store data in the memory cells in a binary format and write data to the selected subset of memory cells by applying a single voltage pulse to the word line.