Semiconductor device and manufacturing method thereof
A semiconductor device comprises a substrate having an N-type field effect transistor (NFET) region and a P-type field effect transistor (PFET) region, a plurality of first nanowires in the PFET region and arranged in a first direction substantially perpendicular to the substrate and a plurality of second nanowires in the NFET region and arranged in the first direction. A composition of the first nanowires is different from a composition of the second nanowires, and one of the first nanowires is substantially aligned with one of the second nanowires in a second direction substantially perpendicular to the first direction.
1. A semiconductor device, comprising:
a substrate having an N-type field effect transistor (NFET) region and a P-type field effect transistor (PFET) region;
a plurality of first nanowires in the PFET region and arranged in a first direction substantially perpendicular to the substrate;
a plurality of second nanowires in the NFET region and arranged in the first direction, wherein a composition of the first nanowires is different from a composition of the second nanowires, and one of the first nanowires is substantially aligned with one of the second nanowires in a second direction substantially perpendicular to the first direction;
a silicon germanium layer in the NFET region and under the second nanowires; and
a gate stack over the silicon germanium layer and surrounding the second nanowires, wherein a first portion of the gate stack is between the silicon germanium layer and a bottommost one of the second nanowires.
2. The semiconductor device of claim 1 , wherein a top surface of the one of the first nanowires and a top surface of the one of the second nanowires are at substantially the same height.
3. The semiconductor device of claim 1 , wherein a bottom surface of the one of the first nanowires and a bottom surface of the one of the second nanowires are at substantially the same height.
4. The semiconductor device of claim 1 , wherein the first nanowires are silicon germanium nanowires, and the second nanowires are silicon nanowires.
5. The semiconductor device of claim 1 , wherein the silicon germanium layer has a top surface in a lower position than a top surface of a second portion of the substrate in the PFET region.
6. The semiconductor device of claim 1 , wherein the silicon germanium layer is in contact with a top surface of a second portion of the substrate in the NFET region.
7. The semiconductor device of claim 1 , wherein the silicon germanium layer is in contact with a gate dielectric layer of the gate stack.
8. The semiconductor device of claim 7 , wherein the silicon germanium layer is in contact with a top surface of a second portion of the substrate in the NFET region.
9. The semiconductor device of claim 1 ,
wherein the first portion of the gate stack is thicker than a bottommost one of the first nanowires.
10. The semiconductor device of claim 1 , wherein a bottommost one of the first nanowires is separated from a second portion of the substrate in the NFET region.
11. The semiconductor device of claim 7 , further comprising:
a source/drain layer over the silicon germanium layer and adjacent to the gate stack, wherein the silicon germanium layer is contact with the source/drain layer.
12. The semiconductor device of claim 11 , wherein the silicon germanium layer is contact with an insulating sidewall between the gate stack and the source/drain layer in the NFET region.
13. A semiconductor device, comprising:
a substrate having a first portion and a second portion thinner than the first portion;
a plurality of first horizontal nanowires over the first portion of the substrate; and
a plurality of second horizontal nanowires over the second portion of the substrate, wherein the second horizontal nanowires comprises a material different from the first horizontal nanowires, and one of the first horizontal nanowires is substantially level with one of the second horizontal nanowires; and
a silicon germanium layer extending along a top surface of the second portion of the substrate and below the second horizontal nanowires; and
an isolation structure embedded in the silicon germanium layer.
14. The semiconductor device of claim 13 , wherein the extension of the silicon germanium layer terminates prior to reaching a top surface of the first portion of the substrate.
15. The semiconductor device of claim 14 , wherein the silicon germanium layer has a top surface in a higher position than the top surface of the first portion of the substrate.
16. The semiconductor device of claim 13 , wherein the silicon germanium layer has a top surface in a lower position than a top surface of the first portion of the substrate.
17. The semiconductor device of claim 13 , wherein the silicon germanium layer is in direct contact with the isolation structure.
18. A semiconductor device, comprising:
a substrate having a first region and a second region;
a germanium-containing layer extending within the second region and terminating prior to reaching the first region;
a plurality of first nanowires horizontally extending above the first region of the substrate and vertically spaced from each other; and
a plurality of second nanowires horizontally extending above the germanium-containing layer and vertically spaced from each other, the second nanowires having a different composition than the germanium-containing layer,
wherein a topmost one of the first nanowires is arranged at an elevation lower than a topmost one of the second nanowires, and at least one of the first nanowires is level with at least one of the second nanowires.
19. The semiconductor device of claim 18 , wherein a bottommost one of the first nanowires is arranged at an elevation lower than a bottommost one of the second nanowires, and at least one of the first nanowires is level with at least one of the second nanowires.
20. The semiconductor device of claim 18 , wherein a bottommost one of the second nanowires is spaced from the germanium-containing layer.