Passivation layer having opening for under bump metallurgy
A semiconductor device includes: a chip having an active surface having connection pads disposed thereon; an encapsulant encapsulating at least portions of the chip; a connection member disposed on the active surface of the chip and including a redistribution layer electrically connected to the connection pads; a passivation layer disposed on the connection member; and an under bump metallurgy (UBM) layer at least partially embedded in the passivation layer and electrically connected to the redistribution layer of the connection member. The UBM layer includes a UBM pad partially embedded in the passivation layer and a UVM via penetrating through a portion of the passivation layer and electrically connecting the redistribution layer of the connection member and the UBM pad to each other. A portion of a side surface of the UBM pad is exposed through an opening formed in the passivation layer and the opening surrounds the UBM pad.
1. An interposer comprising:
a passivation layer;
a first redistribution layer (RDL) disposed on the passivation layer;
under bump metallurgy (UBM) pads at least partially embedded in the passivation layer;
UBM vias penetrating through a portion of the passivation layer and electrically connecting the first RDL and the UBM pads to each other; and
a resin layer disposed on a lower surface of the passivation layer and having openings,
wherein each opening exposes at least a portion of a lower surface of respective UBM pad, and
wherein a width of an upper surface of each UBM via in contact with the redistribution layer is greater than that of a lower surface thereof in contact with the respective UBM pad.
2. The interposer of claim 1 , further comprising:
first connection terminals disposed on the openings,
wherein each first connection terminal is connected to the exposed lower surface of the respective UBM pad.
3. The interposer of claim 1 , further comprising:
an insulating layer disposed on an upper surface of the passivation layer; and
a second RDL disposed on un upper surface of the insulating layer,
wherein the first RDL is embedded in the insulating layer.
4. The interposer of claim 3 , further comprising:
second connection terminals disposed on the upper surface of the insulating layer,
wherein the second RDL includes a plurality of connection terminal pads, and
each second connection terminal is connected to the respective connection terminal pad.
5. The interposer of claim 3 , further comprising:
vias penetrating through at least portions of the insulating layer and electrically connecting the first RDL and the second RDL to each other,
wherein a width of an upper surface of each via in contact with the second RDL is greater than that of a lower surface thereof in contact with the first RDL.
6. The interposer of claim 3 , wherein a lower surface of the insulating layer is disposed on the same level as that of a lower surface of the first RDL.
7. The interposer of claim 1 , wherein a width of a lowermost portion of each opening is greater than that of an uppermost portion thereof.
8. The interposer of claim 1 , wherein the lower surface of the each UBM pad has a step with respect to a lower surface of the resin layer.
9. The interposer of claim 1 , wherein the each UBM via has a reverse trapezoidal cross-sectional shape.
10. The interposer of claim 9 , wherein the each opening has a trapezoidal cross-sectional shape.
11. The interposer of claim 9 , wherein the each UBM via is a filled-via.
12. The interposer of claim 9 , wherein the each UBM pad has a block cross-sectional shape.