Power amplifier for millimeter wave devices

1. A power amplifier, comprising:

a first differential pair of injection transistors comprising a first transistor and a second transistor for receiving a transformer signal;

a first back gate voltage line configured to provide a first back gate voltage to a back gate node of the first transistor;

a second back gate voltage line configured to provide a second back gate voltage to the second transistor;

a second differential pair of oscillator core transistors comprising a third transistor and a fourth transistor and operatively coupled to the first differential pair, wherein the third transistor and the fourth transistor are cross-coupled;

a third back gate voltage line configured to provide a third back gate voltage to the third transistor;

a fourth back gate voltage line configured to provide a fourth back gate voltage to the fourth transistor,

a first back gate voltage source operatively coupled to said first back gate voltage line and configured to provide said first back gate voltage;

a second back gate voltage source operatively coupled to said second back gate voltage line and configured to provide said second back gate voltage;

a third back gate voltage source operatively coupled to said third back gate voltage line and configured to provide said third back gate voltage; and

a fourth back gate voltage source operatively coupled to said fourth back gate voltage line and configured to provide said fourth back gate voltage;

wherein the first back gate voltage, the second back gate voltage, the third back gate voltage, and the fourth back gate voltage are each adjustable.

2. The power amplifier of claim 1 , wherein the first back gate voltage source and the second back gate voltage source are configured to perform at least one of increasing the first back gate voltage and the second back gate voltage to reduce a lock-in time of the first differential pair and decreasing the first back gate voltage and the second back gate voltage to reduce power consumption.

3. The power amplifier of claim 1 , wherein the third back gate voltage source and the fourth back gate voltage source are configured to perform at least one of increasing the third back gate voltage and the fourth back gate voltage to increase output power and adjusting the third back gate voltage and the fourth back gate voltage to compensate current fluctuation.

4. The power amplifier of claim 1 , further comprising an input transformer configured to receive an input signal, wherein the input is at least one of a differential input or a single-ended input.

5. The power amplifier of claim 1 , further comprising an output transformer configured to provide an output signal, wherein the output signal is a differential output.

6. The power amplifier of claim 4 , further comprising a power detector configured to detect the power on each end of the differential output provided by the output transformer.

7. The power amplifier of claim 1 , wherein the first transistor, the second transistor, the third transistor, and the fourth transistor are FDSOI transistors.

8. A method, comprising:

determining a difference between a first power of a first component of a differential output of a power amplifier comprising oscillator core transistors, and a second power of a second component of the differential output;

adjusting a back gate voltage of a first oscillator core transistor, in response to the first power and the second power differing by equal to or greater than a first threshold;

setting the back gate voltage of the first oscillator core transistor to a default value, in response to the back gate voltage being adjusted to a maximum value;

re-determining a difference the first power and the second power, in response to the back gate voltage of the first oscillator core transistor being set to the default value; and

changing a back gate voltage of a second oscillator core transistor, in response to a re-determined difference between the first power and the second power being equal to or greater than a second threshold.

9. The method of claim 8 , wherein the first threshold is 0.1 dB.

10. The method of claim 8 , wherein the second threshold is 0.1 dB.

11. The method of claim 8 , wherein measuring the first power and the second power comprises measuring leakage of the first differential output and the second differential output.

12. A system, comprising:

a semiconductor device processing system to manufacture a semiconductor device; and

a processing controller operatively coupled to said semiconductor device processing system, said processing controller configured to control an operation of the semiconductor device processing system;

wherein the semiconductor device processing system is adapted to:

form an input transformer;

form a first differential pair of injection transistors comprising a first transistor and a second transistor;

form a first back gate voltage source configured to provide a first back gate voltage to the first transistor, wherein the first back gate voltage is adjustable;

form a second back gate voltage source configured to provide a second back gate voltage to the second transistor, wherein the second back gate voltage is adjustable;

form a second differential pair of oscillator core transistors comprising a third transistor and a fourth transistor, wherein the third transistor and the fourth transistor are cross-coupled;

form a third back gate voltage source configured to provide a third back gate voltage to the third transistor, wherein the third back gate voltage is adjustable;

form a fourth back gate voltage source configured to provide a fourth back gate voltage to the fourth transistor, wherein the fourth back gate voltage is adjustable; and

form an output transformer.

13. The system of claim 12 , wherein the semiconductor device processing system is adapted to form a first voltage source to serve as both the first back gate voltage source and the second back gate voltage source, and a second voltage source to serve as both the third back gate voltage source and the fourth back gate voltage source.

14. The system of claim 12 , wherein the semiconductor device processing system is adapted to form the input transformer to receive a differential input.

15. The system of claim 12 , wherein the semiconductor device processing system is adapted to form the output transformer to provide a differential output.

16. The system of claim 15 , wherein the semiconductor device processing system is further adapted to form a power detector configured to detect the power on each end of the differential output provided by the output transformer.

17. The system of claim 16 , wherein the semiconductor device processing system is further adapted to form one or more logic elements configured to perform a method comprising measuring a first power of a first end of the differential output and a second power of a second end of the differential output; and changing at least one of the third back gate voltage and the fourth back gate voltage, in response to the measured first power and the measured second power differing by equal to or greater than a first threshold.

18. The system of claim 12 , wherein the semiconductor device processing system is adapted to form the first transistor, the second transistor, the third transistor, and the fourth transistor as FDSOI transistors.