Nanosheet transistor with robust source/drain isolation from substrate
A substrate structure for a nanosheet transistor includes a plurality of nanosheet layers and a plurality of recesses between the nanosheet layers. The substrate structure includes at least one trench through portions of the nanosheet layers, the sacrificial layers, and the substrate. The substrate structure includes a u-shaped portion formed at a bottom portion of the at least one trench. The u-shaped portion includes a bottom cavity. The substrate structure further includes a first liner disposed upon the u-shaped portion of the at least one trench, and a second liner disposed on the first liner. The substrate structure further includes a third liner disposed within the at least one trench to fill the bottom cavity of the u-shaped portion to form a bottom inner spacer within the bottom cavity.
1. A method of fabricating a nanosheet transistor comprising:
receiving a substrate structure having a plurality of nanosheet layers and a plurality of sacrificial layers stacked upon a substrate;
forming at least one trench through portions of the nanosheet layers, the sacrificial layers, and the substrate;
depositing a first liner within the at least one trench;
depositing a second liner on the first liner;
selectively removing portions of the second liner to form a u-shaped portion at a bottom portion of the at least one trench, the u-shaped portion including a bottom cavity;
selectively removing portions of the first liner to a level of a top portion of the u-shaped portion at the bottom portion of the at least one trench;
selectively laterally etching edges of each of the sacrificial layers to create recesses within the sacrificial layers; and
depositing a third liner within the at least one trench to fill the recesses and the bottom cavity of the u-shaped portion.
2. The method of claim 1 , further comprising:
etching the third liner to form side inner spacers adjacent to the sacrificial layers and a bottom inner spacer within the bottom cavity.
3. The method of claim 2 , further comprising:
depositing a source/drain epitaxy upon the bottom inner spacer.
4. The method of claim 3 , further comprising:
removing portions of the sacrificial layers; and
depositing a gate material within voids left by removal of the sacrificial layers.
5. The method of claim 4 , wherein the gate material includes a high-K metallic gate (HKMG) material.
6. The method of claim 3 , further comprising:
forming a dummy gate upon a top nanosheet layer of the plurality of nanosheet layers.
7. The method of claim 6 , further comprising:
removing portions of the dummy gate; and
depositing a gate material within a void left by removal of the dummy gate.
8. The method of claim 7 , further comprising:
forming an insulative cap upon the gate material;
depositing an interlayer dielectric layer upon the insulative cap; and
forming at least one contact within the interlayer dielectric layer and the insulative cap in contact with the source/drain epitaxy.
9. The method of claim 1 , further comprising:
depositing, prior to selectively removing the second liner, an organic planarizing layer (OPL) within the at least one trench; and
removing the OPL prior to the selective lateral etching of edges of each of the sacrificial layers.
10. The method of claim 1 , wherein the first liner is formed of an oxide material.
11. The method of claim 1 , wherein the second liner is formed of a nitride material.
12. The method of claim 1 , wherein the third liner is formed of a nitride material.
13. The method of claim 1 , wherein the first liner is thinner than the second liner.
14. The method of claim 1 , wherein the nanosheet layers are formed of a silicon (Si) material.
15. The method of claim 1 , wherein the sacrificial layers are formed of a silicon-germanium (SiGe) material.