Under epitaxy isolation structure
Embodiments provide a two-tiered trench isolation structure under the epitaxial regions (e.g., epitaxial source/drain regions) of a nano-FET transistor device, and methods of forming the same. The first tier provides an isolation structure with a low k value. The second tier provides an isolation structure with a higher k value, with material greater density, and greater etch resistivity than the first tier isolation structure.
1 . A method comprising:
forming a multi-layer stack of alternating first semiconductor material layers and second semiconductor material layers over a semiconductor substrate;
patterning the multi-layer stack into a first fin, the first fin having a first lengthwise direction;
forming a dummy gate structure over the first fin, the dummy gate structure having a second lengthwise direction;
etching a first recess in the first fin adjacent the dummy gate structure, the first recess extending into the semiconductor substrate;
depositing a first insulating film in the first recess, the first insulating film having a first k value;
after depositing the first insulating film, depositing a second insulating film in the first recess over the first insulating film, the second insulating film having a second k value, the second k value being greater than the first k value, the second insulating film completely covering the first insulating film and contacting the semiconductor substrate; and
forming an epitaxial region in the first recess over the second insulating film.
2 . The method of claim 1 , further comprising:
after depositing the first insulating film, etching the first insulating film to remove a portion of the first insulating film along sidewalls of the dummy gate structure; and
after depositing the second insulating film, etching the second insulating film to remove a portion of the second insulating film along sidewalls of the dummy gate structure.
3 . The method of claim 2 , wherein after etching the second insulating film, a portion of the first insulating film or the second insulating film remains over the dummy gate structure.
4 . The method of claim 1 , further comprising:
forming a sidewall spacer in the first recess along a sidewall of a first layer of the first fin, wherein forming the epitaxial region comprises forming a first epitaxial layer on the sidewall spacer, a surface of the first epitaxial layer having a curved surface opposite a sidewall of the sidewall spacer, and forming a second epitaxial layer over the first epitaxial layer.
5 . The method of claim 4 , wherein after forming the epitaxial region, the second insulating film has an interface with the sidewall spacer.
6 . The method of claim 1 , wherein the first fin comprises a fin portion of the multi-layer stack over a fin portion of the semiconductor substrate, wherein the first recess exposes the fin portion of the semiconductor substrate, wherein after forming the epitaxial region, the first insulating film completely covers the fin portion of the semiconductor substrate.
7 . The method of claim 1 , wherein depositing the first insulating film is done at a processing temperature which is lower than a processing temperature used to deposit the second insulating film.
8 . The method of claim 1 , wherein the second insulating film is denser than the first insulating film.
9 . A method comprising:
forming first nanostructures and second nanostructures over a substrate, each of the first nanostructures alternating with each of the second nanostructures, wherein the substrate, the first nanostructures, and the second nanostructures are stacked to form a first fin;
forming a dummy gate structure over the first fin;
forming a recess in the first fin adjacent the dummy gate structure, the recess continuing through the first nanostructures, the second nanostructures, and exposing the substrate;
depositing a first insulating layer in the recess and over the dummy gate structure;
after depositing the first insulating layer, etching the first insulating layer to form a first isolation structure at a bottom of the recess;
after etching the first insulating layer, depositing a second insulating layer in the recess over the first isolation structure and over the dummy gate structure; and
etching the second insulating layer to form a second isolation structure over the first isolation structure, wherein an etch resistance of the second insulating layer is different from an etch resistance of the first insulating layer, wherein the second isolation structure contacts the substrate, wherein a top surface of a center portion of the second isolation structure is lower than a top surface of the substrate.
10 . The method of claim 9 , wherein the second insulating layer is deposited with a lesser oxygen content than the first insulating layer.
11 . The method of claim 9 , further comprising:
forming sidewall spacers on sidewalls of a base nanostructure of the first nanostructures, wherein after forming the second isolation structure a portion of the second isolation structure contacts the sidewall spacers.
12 . The method of claim 11 , further comprising:
depositing a first portion of a first layer of an epitaxial region on the sidewall spacers and a second portion of the first layer of the epitaxial region on the second isolation structure, the first portion having a curved surface opposite a sidewall of the sidewall spacers, the second portion having a curved surface opposite an interface with the second isolation structure, wherein the first portion is merged with the second portion; and
depositing a second layer of the epitaxial region over the first layer of the epitaxial region, the second layer filling the recess.
13 . A method comprising:
forming a first fin protruding from a substrate, the first fin having a first lengthwise direction;
forming a dummy gate structure over the first fin, the dummy gate structure having a second lengthwise direction;
etching a first recess in the first fin adjacent the dummy gate structure, the first recess extending into the substrate;
depositing a first insulating film in the first recess, the first insulating film being a first dielectric material, wherein after depositing the first insulating film a portion of the substrate is exposed in the first recess;
after depositing the first insulating film, depositing a second insulating film in the first recess over the first insulating film, the second insulating film being a second dielectric material different than the first dielectric material, wherein the second dielectric material covers the first insulating film, wherein the second dielectric material contacts the substrate; and
forming an epitaxial region in the first recess over the second insulating film, wherein the second insulating film separates the epitaxial region from the first insulating film.
14 . The method of claim 13 , wherein the second dielectric material has a k value greater than the first dielectric material.
15 . The method of claim 13 , wherein an oxygen content of the first insulating film is greater than an oxygen content of the second insulating film.
16 . The method of claim 13 , wherein a ratio of a first thickness of the first insulating film to a second thickness of the second insulating film is between 2:1 and 1:1.
17 . The method of claim 13 , wherein the first fin includes alternating layers of a first material and a second material over the substrate, wherein the first insulating film is recessed below an upper surface of the substrate.
18 . The method of claim 17 , wherein an upper surface of the second insulating film is above the upper surface of the substrate.
19 . The method of claim 17 , further comprising:
after etching the first recess and prior to depositing the first insulating film, recessing a sidewall of a first layer of the first material to form a second recess; and
forming an inner spacer in the second recess.
20 . The method of claim 1 , further comprising:
prior to depositing the first insulating film, recessing a sidewall of a first layer of the multi-layer stack; and
forming an inner spacer along the sidewall of the first layer of the multi-layer stack.