Semiconductor device and method of packaging
A semiconductor device may comprise a semiconductor die comprising an active surface and contact pads disposed. Conductive interconnects comprising first ends may be coupled to the contact pads and second ends may be disposed opposite the first ends. An encapsulant may comprise a planar surface disposed over the active surface of the semiconductor die. The planar surface may be offset from the second surface of the conductive interconnects by a distance greater than or equal to 1 micrometer. A build-up interconnect layer may be disposed over the planar surface and extend into the openings to electrically connect with the conductive interconnects. A method of making the semiconductor device may further comprise grinding a surface of the encapsulant to form the planar surface and the conductive residue across the planar surface. The conductive residue may be etched to remove the conductive residue and to reduce a height of the conductive interconnects.
1. A semiconductor device comprising:
a semiconductor die comprising four side surfaces and an active surface, the semiconductor die further comprising contact pads disposed over the active surface;
conductive interconnects comprising first ends coupled to the contact pads, second ends opposite the first ends, and side surfaces extending between the first ends and the second ends, the second ends of the conductive interconnects offset from the active surface by a height of at least 8 micrometers (μm);
a single encapsulant contacting the four side surfaces of the semiconductor die and side surfaces of the conductive interconnects, the single encapsulant further comprising a planar surface disposed over the active surface of the semiconductor die, the planar surface being offset from the active surface by more than the height of the conductive interconnects;
openings formed through the planar surface of the single encapsulant and extending to the second ends of the conductive interconnects, the openings comprising a depth greater than or equal to 1 μm; and
a build-up interconnect layer disposed over the planar surface and comprising a fan-out redistribution layer (RDL) extending into the openings to electrically connect with the conductive interconnects.
2. The semiconductor device of claim 1 , wherein the conductive interconnects comprise copper studs or redistribution layer (RDL) traces.
3. The semiconductor device of claim 1 , wherein the build-up interconnect layer comprises conductive bumps coupled to the redistribution layer (RDL).
4. The semiconductor device of claim 1 , wherein the planar surface is free from a conductive residue formed by grinding the single encapsulant and the conductive interconnects.
5. The semiconductor device of claim 1 , further comprising a backside coating contacting a backside of the semiconductor die.
6. A method of making the semiconductor device of claim 4 , further comprising:
grinding a surface of the single encapsulant to expose the conductive interconnects, to form the planar surface, and to form the conductive residue across the planar surface; and
etching the conductive residue and the exposed conductive interconnects to remove the conductive residue at the planar surface and to reduce a height of the conductive interconnects to form the second ends of the conductive interconnects offset from the planar surface by a distance greater than 1 μm.
7. A semiconductor device comprising:
a semiconductor die comprising four side surfaces and an active surface, the semiconductor die further comprising contact pads disposed over the active surface;
conductive interconnects comprising first ends coupled to the contact pads and second ends opposite the first ends;
a single encapsulant contacting the four side surfaces of the semiconductor die and side surfaces of the conductive interconnects, the single encapsulant further comprising a planar surface disposed over the active surface of the semiconductor die, the planar surface being offset from the active surface by more than the height of the conductive interconnects;
openings formed through the planar surface of the single encapsulant and extending to the second ends of the conductive interconnects, the openings comprising a depth greater than or equal to 1 micrometers (μm); and
a build-up interconnect layer disposed over the planar surface and comprising a fan-out redistribution layer (RDL) extending into the openings to electrically connect with the conductive interconnects.
8. The semiconductor device of claim 7 , wherein the conductive interconnects comprise copper studs or redistribution layer (RDL) traces.
9. The semiconductor device of claim 7 , wherein the build-up interconnect layer comprises conductive bumps coupled to the redistribution layer (RDL).
10. The semiconductor device of claim 7 , wherein the planar surface is free from a conductive residue formed by grinding the single encapsulant and the conductive interconnects.
11. The semiconductor device of claim 7 , further comprising a backside coating contacting a backside of the semiconductor die.
12. A method of making the semiconductor device of claim 10 , further comprising:
grinding a surface of the single encapsulant to expose the conductive interconnects, to form the planar surface, and to form the conductive residue across the planar surface; and
etching the conductive residue and the exposed conductive interconnects to remove the conductive residue at the planar surface and to reduce a height of the conductive interconnects to form the second ends of the conductive interconnects offset from the planar surface by a distance greater than 1 μm.
13. The semiconductor device of claim 9 , wherein a back surface of the semiconductor die is exposed at a periphery of the semiconductor device.
14. A semiconductor device comprising:
a semiconductor die comprising an active surface and contact pads disposed over the active surface;
conductive interconnects comprising first ends coupled to the contact pads and second ends opposite the first ends;
an encapsulant comprising a planar surface disposed over the active surface of the semiconductor die, the encapsulant comprising openings with a distance greater than or equal to 1 micrometer (μm) that extend from the planar surface of the encapsulant to the conductive interconnects; and
a build-up interconnect layer disposed over the planar surface and comprising a fan-out redistribution layer (RDL) extending across the planar surface of the encapsulant and into the openings to electrically connect with the conductive interconnects.
15. The semiconductor device of claim 14 , wherein the conductive interconnects comprise copper studs or redistribution layer (RDL) traces.
16. The semiconductor device of claim 14 , wherein a back surface of the semiconductor die is exposed at a periphery of the semiconductor device.
17. The semiconductor device of claim 14 , wherein the planar surface is free from a conductive residue formed by grinding the encapsulant and the conductive interconnects.
18. The semiconductor device of claim 14 , further comprising a backside coating contacting a backside of the semiconductor die.
19. A method of making the semiconductor device of claim 17 , further comprising:
grinding a surface of the encapsulant to expose the conductive interconnects, to form the planar surface, and to form the conductive residue across the planar surface; and
etching the conductive residue and the exposed conductive interconnects to remove the conductive residue at the planar surface and to reduce a height of the conductive interconnects to form the second ends of the conductive interconnects offset from the planar surface by a distance greater than 1 μm.
20. The semiconductor device of claim 14 , wherein:
the semiconductor die comprises four side surfaces;
the conductive interconnects comprise side surfaces extending from the first ends to the second ends; and
the encapsulant contacts the four side surfaces of the semiconductor die and the side surfaces of the conductive interconnects.