IP Library Granted Patent US 10,475,987
Granted Patent B1
US 10,475,987 · App. 15/968,035 · Granted Nov 12, 2019

Method for fabricating a magnetic tunneling junction (MTJ) structure

Inventors: Jesmin Haq (Milpitas, CA); Tom Zhong (Saratoga, CA); Vinh Lam (Dublin, CA); Vignesh Sundar (Sunnyvale, CA); Zhongjian Teng (Santa Clara, CA)
Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
H01L43/02G11B5/4826G11B5/6082G11B19/2009H01L43/12
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Quick Facts
Patent No.
US 10,475,987
App. No.
15/968,035
Granted
Nov 12, 2019
Kind
B1
Abstract

A method for fabricating an improved magnetic tunneling junction (MTJ) structure is described. A bottom electrode is provided on a substrate. A MTJ stack is deposited on the bottom electrode. A top electrode is deposited on the MTJ stack. A first stress modulating layer is deposited between the bottom electrode and the MTJ stack, or a second stress modulating layer is deposited between the MTJ stack and the top electrode, or both a first stress modulating layer is deposited between the bottom electrode and the MTJ stack and a second stress modulating layer is deposited between the MTJ stack and the top electrode. The top electrode and MTJ stack are patterned and etched to form a MTJ device. The stress modulating layers reduce crystal growth defects and interfacial defects during annealing and improve the interface lattice epitaxy. This will improve device performance.

Claims (31)

1. A method, comprising:

forming a first stress modulating layer on a first electrode layer, wherein a material of the first stress modulating layer is different from a material of the first electrode layer;

forming a magnetic tunneling junction (MTJ) material stack on the first stress modulating layer;

forming a second stress modulating layer on the MTJ material stack;

forming a second electrode layer on the second stress modulating layer, wherein a material of the second stress modulating layer is different from a material of the second electrode layer; and

annealing the first stress modulating layer, the MTJ material stack, the second stress modulating layer, and the second electrode layer.

2. The method of claim 1 , wherein a lattice stress generated in the first electrode layer by the annealing is released through the first stress modulating layer, and wherein a lattice stress generated in the second electrode layer by the annealing is released through the second stress modulating layer.

3. The method of claim 1 , wherein each of the first stress modulating layer and the second stress modulating layer includes a material selected from the group consisting of Mg, Al, Hf, Zr, and a combination thereof.

4. The method of claim 1 , wherein a thickness of each of the first stress modulating layer and the second stress modulating layer is from about 1 nanometer to about 100 nanometers.

5. The method of claim 4 , wherein the thickness of each of the first stress modulating layer and the second stress modulating layer is about 10 nanometers.

6. The method of claim 1 , wherein an elastic modulus of each of the first stress modulating layer and the second stress modulating layer is from about 20 Gigapascals (GPa) to about 400 GPa.

7. The method of claim 6 , wherein the elastic modulus of each of the first stress modulating layer and the second stress modulating layer is about 50 GPa.

8. A method, comprising:

encapsulating a bottom electrode in a dielectric material layer, wherein a top surface of the bottom electrode is coplanar with a top surface of the dielectric material layer;

forming a first stress modulating layer over the dielectric material layer and the bottom electrode;

forming a magnetic tunneling junction (MTJ) stack over the first stress modulating layer;

forming a second stress modulating layer over the MTJ stack;

forming a hard mask layer over the second stress modulating layer; and

patterning the second stress modulating layer, the MTJ stack, and the first stress modulating layer, wherein the patterning exposes the dielectric material layer and a portion of the top surface of the bottom electrode, and wherein a lattice stress generated in the MTJ stack during the patterning is released through the first stress modulating layer and the second stress modulating layer.

9. The method of claim 8 , further comprising forming a top electrode over the second stress modulating layer.

10. The method of claim 8 , wherein forming the MTJ stack includes:

depositing a seed layer on the first stress modulating layer, the seed layer physically contacting the first stress modulating layer;

depositing a pinned layer on the seed layer;

depositing a barrier layer on the pinned layer;

depositing a free layer on the barrier layer; and

depositing a capping layer on the free layer.

11. The method of claim 10 , wherein the second stress modulating layer physically contacts the capping layer of the MTJ stack.

12. The method of claim 8 , wherein an elastic modulus of each of the first stress modulating layer and the second stress modulating layer is from about 20 Gigapascals (GPa) to about 400 GPa.

13. The method of claim 12 , wherein the elastic modulus of each of the first stress modulating layer and the second stress modulating layer is about 50 GPa.

14. The method of claim 8 , wherein a thickness of each of the first stress modulating layer and the second stress modulating layer is from about 1 nanometer to about 100 nanometers.

15. The method of claim 8 , wherein each of the first stress modulating layer and the second stress modulating layer includes a material selected from the group consisting of Mg, Al, Hf, Zr, and a combination thereof.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 25, 2019
From: HEADWAY TECHNOLOGIES, INC.
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 048692/0917 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 13, 2018
From: HAQ, JESMIN; ZHONG, TOM; LAM, VINH; SUNDAR, VIGNESH; TENG, ZHONGJIAN
To: HEADWAY TECHNOLOGIES, INC
Reel/Frame 046066/0347 →
Cited By (1)
US 12,207,566