Singulation of silicon carbide semiconductor wafers
A method of singulating a silicon carbide (SiC) semiconductor wafer can include defining a cut within the silicon carbide (SiC) semiconductor wafer by performing a partial dicing operation where the SiC semiconductor wafer is aligned along a plane and the cut has a depth less than a first thickness of the SiC semiconductor wafer. The cut is aligned along a vertical direction orthogonal to the plane such that a portion of the SiC semiconductor wafer has a second thickness that extends between a bottom of the cut and an outer surface of the SiC semiconductor wafer. The method can further include defining a cleave, by performing a cleaving operation, through the portion of the SiC semiconductor wafer having the second thickness. The cleave can be aligned with the cut and extending to the outer surface of the SiC semiconductor wafer.
1. A method, comprising:
defining a cut within a silicon carbide (SiC) semiconductor wafer by performing a partial dicing operation on a first surface of the silicon carbide (SiC) semiconductor wafer, the silicon carbide (SiC) semiconductor wafer being aligned along a plane, the cut having a depth less than a first thickness of the silicon carbide (SiC) semiconductor wafer, the cut being aligned along a vertical direction orthogonal to the plane such that a portion of the silicon carbide (SiC) semiconductor wafer has a second thickness that extends between a bottom of the cut and an outer surface of the silicon carbide (SiC) semiconductor wafer; and
defining a cleave, by performing a cleaving operation on a second surface of the silicon carbide (SiC) semiconductor wafer, through the portion of the silicon carbide (SiC) semiconductor wafer having the second thickness, the cleave being aligned along the vertical direction and being aligned with the cut and extending to the outer surface of the silicon carbide (SiC) semiconductor wafer, the second surface being opposite the first surface.
2. The method of claim 1 , wherein the depth of the cut is between 65% and 75% of the first thickness.
3. The method of claim 1 , wherein the cut has a first width in a direction parallel to the plane and the cleave has a second width in the direction parallel to the plane, the first width being greater than the second width;
the cut and the cleave are used to define a set of SiC die, each of the set of SiC die having a step, the step having a width in the direction parallel to the plane based on a difference between the first width and the second width.
4. The method of claim 3 , further comprising:
prior to performing the cleaving operation, performing a backmetal deposition operation on the silicon carbide (SiC) semiconductor wafer.
5. The method of claim 1 , wherein performing the cleaving operation includes:
applying a cleaving force to the silicon carbide (SiC) semiconductor wafer along the cut using an impulse bar.
6. The method of claim 1 , wherein the performing the partial dicing operation includes:
receiving the silicon carbide (SiC) semiconductor wafer by a laser ablation tool; and
defining a power of the laser ablation tool to enable the laser ablation tool to define the cut having the depth.
7. The method of claim 1 , wherein the performing the partial dicing operation includes:
receiving the silicon carbide (SiC) semiconductor wafer by a mechanical saw tool, the mechanical saw tool including a saw blade; and
defining a position of the saw blade to define the cut having the depth.
8. A method, comprising:
thinning a silicon carbide (SiC) semiconductor wafer to a thickness, a surface of the SiC semiconductor wafer aligned along a plane;
performing a partial dicing operation on a first surface of the silicon carbide (SiC) semiconductor wafer to define a cut in the silicon carbide (SiC) semiconductor wafer through a first portion of the thickness of the silicon carbide (SiC) semiconductor wafer, the cut aligned along a vertical direction orthogonal to the plane, the cut aligned such that a portion of the silicon carbide (SiC) semiconductor wafer has a second thickness that extends between a bottom of the cut and an outer surface of the silicon carbide (SiC) semiconductor wafer, the cut also having a first width in a direction parallel to the plane; and
performing a cleaving operation on a second surface of the silicon carbide (SiC) semiconductor wafer to define a cleave having a second width less than the first width, the cleave aligned with the cut and through a second portion of the thickness of the silicon carbide (SiC) semiconductor wafer, the second surface being opposite the first surface.
9. The method of claim 8 , wherein the cut and the cleave are used to define a set of SiC die, each of the set of SiC die having a step, the step having a width in the direction parallel to the plane based on a difference between the first width and the second width.
10. The method of claim 8 , wherein the first portion of the thickness of the silicon carbide (SiC) semiconductor wafer is between 65% and 75% of the thickness of the silicon carbide (SiC) semiconductor wafer.
11. The method of claim 8 , wherein the partial dicing operation is performed by a laser ablation tool, and wherein performing the partial dicing operation includes:
adjusting at least one of a power or a number of passes of the laser ablation tool to enable the laser ablation tool to define the cut through the first portion of the thickness of the silicon carbide (SiC) semiconductor wafer.
12. The method of claim 8 , wherein the partial dicing operation is performed by a mechanical saw tool, and wherein performing the partial dicing operation includes:
adjusting a position of a saw blade of the mechanical saw tool to enable the mechanical saw tool to define a depth of the cut.