Fan-out semiconductor package
A fan-out semiconductor package includes: a frame including insulating layers, wiring layers, and connection via layers, and having a recess portion and a stopper layer disposed on a bottom surface of the recess portion; a semiconductor chip disposed in the recess portion, and having connection pads, an active surface on which the connection pads are disposed, and an inactive surface opposing the active surface and disposed on the stopper layer; an encapsulant covering at least portions of the semiconductor chip and filling at least portions of the recess portion; and a connection member disposed on the frame and the active surface of the semiconductor chip and including a redistribution layer electrically connecting the plurality of wiring layers of the frame and the connection pads of the semiconductor chip to each other. The active surface of the semiconductor chip and an upper surface of the encapsulant have a step portion therebetween.
1. A fan-out semiconductor package comprising:
a frame including a plurality of insulating layers, a plurality of wiring layers disposed on the plurality of insulating layers, and a plurality of connection via layers penetrating through the plurality of insulating layers and electrically connecting the plurality of wiring layers to each other, and having a recess portion and a stopper layer disposed on a bottom surface of the recess portion;
a semiconductor chip disposed in the recess portion, and having connection pads, an active surface on which the connection pads are disposed, and an inactive surface opposing the active surface and disposed on the stopper layer;
an encapsulant covering at least portions of the semiconductor chip and filling at least portions of the recess portion; and
a connection member disposed on the frame and the active surface of the semiconductor chip and including a redistribution layer electrically connecting the plurality of wiring layers of the frame and the connection pads of the semiconductor chip to each other,
wherein the active surface of the semiconductor chip and an upper surface of the encapsulant have a step portion therebetween.
2. The fan-out semiconductor package of claim 1 , wherein the connection member includes an insulating layer disposed on the frame, the encapsulant, and the active surface of the semiconductor chip, the redistribution layer disposed on the insulating layer, first connection vias penetrating through the insulating layer and electrically connecting the redistribution layer and the connection pads to each other, and second connection vias penetrating through the insulating layer and electrically connecting the redistribution layer and an uppermost wiring layer of the plurality of wiring layers of the frame to each other, and
a boundary surface between the insulating layer of the connection member and the encapsulant has a step portion with respect to a boundary surface between the insulating layer of the connection member and the active surface of the semiconductor chip.
3. The fan-out semiconductor package of claim 2 , wherein the first connection vias are in direct contact with the connection pads.
4. The fan-out semiconductor package of claim 2 , wherein in a direction perpendicular to the active surface of the semiconductor chip, a thickness of the insulating layer of the connection member in a fan-in region is different from that of the insulating layer of the connection member in a fan-out region.
5. The fan-out semiconductor package of claim 4 , wherein the thickness of the insulating layer of the connection member in the fan-in region is greater than that of the insulating layer of the connection member in the fan-out region.
6. The fan-out semiconductor package of claim 2 , wherein the first and second connection vias have different heights.
7. The fan-out semiconductor package of claim 6 , wherein the first connection via has a height greater than that of the second connection via.
8. The fan-out semiconductor package of claim 2 , wherein the insulating layer of the connection member includes a photoimagable dielectric (PID).
9. The fan-out semiconductor package of claim 1 , wherein the plurality of insulating layers include a core insulating layer, one or more first build-up insulating layers disposed on a lower surface of the core insulating layer, and one or more second build-up insulating layers disposed on an upper surface of the core insulating layer, and
the core insulating layer has a thickness greater than that of each of the first and second build-up insulating layers.
10. The fan-out semiconductor package of claim 9 , wherein the number of first build-up insulating layers and the number of second build-up insulating layers are the same as each other.
11. The fan-out semiconductor package of claim 9 , wherein the recess portion penetrates through at least the core insulating layer and penetrates through at least one of the one or more second build-up insulating layers.
12. The fan-out semiconductor package of claim 11 , wherein a number of the one or more first build-up insulating layers is two or greater, and
the recess portion further penetrates one or more of the one or more first build-up insulating layers, but not penetrates through a lowermost one of the one or more first build-up insulating layer.
13. The fan-out semiconductor package of claim 9 , wherein first connection vias penetrating through the first build-up insulating layer and second connection vias penetrating through the second build-up insulating layer are tapered in opposite directions to each other.
14. The fan-out semiconductor package of claim 1 , wherein walls of the recess portion are tapered.
15. The fan-out semiconductor package of claim 1 , wherein the inactive surface of the semiconductor chip is attached to the stopper layer through an adhesive member.
16. The fan-out semiconductor package of claim 1 , wherein the stopper layer is a metal layer,
at least one of the plurality of wiring layers includes a ground, and
the metal layer is electrically connected to the ground.
17. The fan-out semiconductor package of claim 1 , wherein the stopper layer has a planar area greater than that of the inactive surface of the semiconductor chip.
18. The fan-out semiconductor package of claim 1 , wherein the bottom surface of the recess portion has a planar area greater than that of the inactive surface of the semiconductor chip.
19. The fan-out semiconductor package of claim 1 , wherein a region of the stopper layer exposed by the recess portion has a thickness smaller than that of an edge region of the stopper layer that is not exposed by the recess portion.
20. The fan-out semiconductor package of claim 1 , wherein an upper surface of an uppermost wiring layer of the plurality of wiring layers of the frame or an uppermost connection via layer of the plurality of connection via layers of the frame is coplanar with the upper surface of the encapsulant.
21. The fan-out semiconductor package of claim 1 , further comprising:
a first passivation layer disposed on the connection member and having openings exposing at least portions of the redistribution layer;
underbump metal layers disposed in the openings of the first passivation layer and connected to at least portions of the exposed redistribution layer; and
electrical connection structures disposed on the first passivation layer and connected to the underbump metal layers.
22. The fan-out semiconductor package of claim 21 , further comprising a second passivation layer disposed beneath the frame and having openings exposing at least portions of a lowermost wiring layer of the plurality of wiring layers.
23. The fan-out semiconductor package of claim 1 , wherein the active surface of the semiconductor chip is not covered by the encapsulant.
24. The fan-out semiconductor package of claim 1 , wherein at least one of the wiring layers are disposed on the level below the stopper layer.