Fan-out semiconductor package

1. A fan-out semiconductor package comprising:

a frame including a plurality of insulating layers, a plurality of wiring layers each disposed on the plurality of insulating layers, and a plurality of connection via layers penetrating through the plurality of insulating layers and electrically connecting the plurality of wiring layers to each other, and having a recess portion having a stopper layer beneath a top surface thereof;

a semiconductor chip having an active surface, on which connection pads are disposed, and an inactive surface opposing the active surface, the semiconductor chip being disposed on a first surface of the frame and disposed in the recess portion so that the inactive surface is connected to the stopper layer;

a first encapsulant covering at least portions of the semiconductor chip and filling at least portions of the recess portion;

an electronic component;

a second encapsulant covering at least portions of the electronic component; and

a connection member disposed on the first surface of the frame and the active surface of the semiconductor chip, and including one or more redistribution layers,

wherein the connection pads of the semiconductor chip and the electronic component are electrically connected to each other through the plurality of wiring layers of the frame and the one or more redistribution layers of the connection member,

wherein the connection member further includes one or more connection vias connecting the one or more redistribution layers of the connection member and a lowermost wiring layer of the plurality of wiring layers of the frame,

wherein the connection pads of the semiconductor chip and uppermost vias of the one or more connection vias of the connection member are connected to each other through metal bumps, and

wherein at respective interfaces between the metal bumps and the uppermost vias, surface areas of the metal bumps and the uppermost vias are different from each other.

2. The fan-out semiconductor package of claim 1 , wherein the electronic component is a semiconductor chip having an active surface, on which connection pads are disposed, and an inactive surface opposing the active surface, the active surface facing the second surface of the frame.

3. The fan-out semiconductor package of claim 1 , wherein the plurality of insulating layers include a core insulating layer, one or more first build-up insulating layers disposed on an upper surface of the core insulating layer, and one or more second build-up insulating layers disposed on a lower surface of the core insulating layer, and

a thickness of the core insulating layer is greater than that of each of the first and second build-up insulating layers.

4. The fan-out semiconductor package of claim 3 , wherein the number of first build-up insulating layers is the same as the number of second build-up insulating layers.

5. The fan-out semiconductor package of claim 3 , wherein the recess portion penetrates through at least a portion of the core insulating layer and penetrates through at least one of the one or more first and second build-up insulating layers.

6. The fan-out semiconductor package of claim 1 , wherein a region of the stopper layer contacting the recess portion has a thickness smaller than that of an edge region of the stopper layer that does not contact the recess portion.

7. The fan-out semiconductor package of claim 1 , wherein the metal bumps are disposed on the connection pads of the semiconductor chip, and

lower surfaces of the metal bumps are coplanar with a lower surface of the first encapsulant.

8. The fan-out semiconductor package of claim 7 , wherein a lower surface of the lowermost wiring layer of the plurality of wiring layers of the frame or a lower surface of a lowermost connection via layer of the plurality of connection via layers of the frame is coplanar with the lower surfaces of the metal bumps and the lower surface of the first encapsulant.

9. The fan-out semiconductor package of claim 3 , wherein first connection via layers penetrating through the one or more first build-up insulating layers and second connection via layers penetrating through the one or more second build-up insulating layers are tapered in opposite directions to each other.

10. The fan-out semiconductor package of claim 1 , wherein walls of the recess portion are tapered.

11. The fan-out semiconductor package of claim 1 , wherein the inactive surface of the semiconductor chip is attached to the stopper layer through an adhesive member.

12. The fan-out semiconductor package of claim 1 , wherein the stopper layer is a metal layer,

at least one of the plurality of wiring layers includes a ground, and

the metal layer is electrically connected to the ground.

13. The fan-out semiconductor package of claim 1 , wherein the stopper layer has a planar area larger than the inactive surface of the semiconductor chip.

14. The fan-out semiconductor package of claim 1 , wherein the top surface of the recess portion has a planar area larger than the inactive surface of the semiconductor chip.

15. The fan-out semiconductor package of claim 1 , further comprising:

a first passivation layer disposed beneath the connection member and having openings exposing at least portions of the one or more redistribution layers;

underbump metal layers disposed in the openings of the first passivation layer and connected to at least portions of the exposed one or more redistribution layers; and

electrical connection structures disposed beneath the first passivation layer and connected to the underbump metal layers.

16. The fan-out semiconductor package of claim 15 , further comprising a second passivation layer disposed on the frame and having openings exposing at least portions of an uppermost wiring layer of the plurality of wiring layers,

wherein the electric component is surface-mounted on the second passivation layer.

17. The fan-out semiconductor package of claim 1 , wherein the semiconductor chip is an application processor (AP) chip, and

the electronic component is a dynamic random access memory (DRAM) chip.

18. The fan-out semiconductor package of claim 17 , wherein the electronic component is a plurality of DRAM chips disposed in parallel with each other.

19. A fan-out semiconductor package comprising:

a frame including a plurality of insulating layers, a plurality of wiring layers each disposed on the plurality of insulating layers, and a plurality of connection via layers penetrating through the plurality of insulating layers and electrically connecting the plurality of wiring layers to each other, and having a recess portion on a first surface of the frame;

a semiconductor chip, disposed in the recess portion, having an active surface, on which connection pads are disposed, and an inactive surface opposing the active surface;

a first encapsulant covering at least portions of the semiconductor chip and filling at least portions of the recess portion;

an electronic component;

a second encapsulant covering at least portions of the electronic component; and

a connection member disposed on the first surface of the frame and the active surface of the semiconductor chip, and including one or more redistribution layers,

wherein the connection pads of the semiconductor chip and the electronic component are electrically connected to each other through the plurality of wiring layers of the frame and the one or more redistribution layers of the connection member,

wherein the recess portion has one surface covered with a stopper layer and another surface opposing the one surface being opened,

wherein the electronic component is directly connected to the plurality of wiring layers of the frame through metal bumps, and

wherein at least one of the plurality of wiring layers is disposed on a same level as the stopper layer.

20. The fan-out semiconductor package of claim 19 , wherein

the electronic component is at least one semiconductor chip having an active surface, on which connection pads are disposed, and an inactive surface opposing the active surface, the active surface facing the second surface of the frame, and

the metal bumps are in contact with the connection pads of the electronic component and the plurality of wiring layers of the frame.

21. The fan-out semiconductor package of claim 1 , wherein at least one of the plurality of wiring layers is disposed on a level above the stopper layer.

22. A fan-out semiconductor package comprising:

a frame including a plurality of insulating layers, a plurality of wiring layers each disposed on the plurality of insulating layers, and a plurality of connection via layers penetrating through the plurality of insulating layers and electrically connecting the plurality of wiring layers to each other, and having a recess portion having a stopper layer beneath a top surface thereof;

a semiconductor chip having an active surface, on which connection pads are disposed, and an inactive surface opposing the active surface, the semiconductor chip being disposed on a first surface of the frame and disposed in the recess portion so that the inactive surface is connected to the stopper layer;

a first encapsulant covering at least portions of the semiconductor chip and filling at least portions of the recess portion;

an electronic component;

a second encapsulant covering at least portions of the electronic component;

a connection member disposed on the first surface of the frame and the active surface of the semiconductor chip, and including one or more redistribution layers;

a first passivation layer disposed beneath the connection member and having openings exposing at least portions of the one or more redistribution layers;

underbump metal layers disposed in the openings of the first passivation layer and connected to at least portions of the exposed one or more redistribution layers; and

electrical connection structures disposed beneath the first passivation layer and connected to the underbump metal layers,

wherein the connection pads of the semiconductor chip and the electronic component are electrically connected to each other through the plurality of wiring layers of the frame and the one or more redistribution layers of the connection member.