Hybrid gate dielectrics for semiconductor power devices
In a general aspect, a power semiconductor device can include a silicon carbide (SiC) substrate and a SiC epitaxial layer disposed on the SiC substrate. The device can include a well region disposed in the epitaxial layer, a source region disposed in the well region and a gate trench disposed in the epitaxial layer and adjacent to the source region. The gate trench can have a depth that is greater than a depth of the well region and less than a depth of the epitaxial layer. The device can include a hybrid gate dielectric disposed on a sidewall of the gate trench and a bottom surface of the gate trench. The hybrid gate dielectric can include a first high-k material and a second high-k dielectric material that is different than the first high-k dielectric material. The device can include a conductive gate electrode disposed on the hybrid gate dielectric.
1. A power semiconductor device comprising:
a silicon carbide (SiC) substrate of a first conductivity type;
a SiC epitaxial layer of the first conductivity type disposed on the SiC substrate, the SiC epitaxial layer having a doping concentration that is different than a doping concentration of the SiC substrate;
a well region of a second conductivity type disposed in the SiC epitaxial layer;
a source region of the first conductivity type disposed in the well region;
a gate trench disposed in the SiC epitaxial layer and adjacent to the source region, the gate trench having a depth that is greater than a depth of the well region and that is less than a depth of the SiC epitaxial layer;
a gate structure including:
a hybrid gate dielectric disposed on a sidewall of the gate trench and a bottom surface of the gate trench, the hybrid gate dielectric including a first high-k dielectric material and a second high-k dielectric material that is different than the first high-k dielectric material;
an interface dielectric layer disposed between the hybrid gate dielectric and the SiC epitaxial layer, the interface dielectric layer including a thermally grown silicon dioxide (SiO 2 ) layer that fully separates the hybrid gate dielectric from the SiC epitaxial layer; and
a conductive gate electrode disposed on the hybrid gate dielectric.
2. The power semiconductor device of claim 1 , wherein:
the first high-k dielectric material is included in a first layer of the hybrid gate dielectric that is disposed on the sidewall of the gate trench and the bottom surface of the gate trench; and
the second high-k dielectric material is included in a second layer of the hybrid gate dielectric that is disposed on the first layer of the hybrid gate dielectric.
3. The power semiconductor device of claim 1 , wherein the hybrid gate dielectric includes a composite of the first high-k dielectric material and the second high-k dielectric material.
4. The power semiconductor device of claim 3 , wherein respective concentrations of the first high-k dielectric material and the second high-k dielectric material vary across a thickness of the hybrid gate dielectric.
5. The power semiconductor device of claim 1 , wherein the hybrid gate dielectric further includes a third high-k dielectric material.
6. The power semiconductor device of claim 5 , wherein:
the first high-k dielectric material is included in a first layer of the hybrid gate dielectric that is disposed on the sidewall of the gate trench and the bottom surface of the gate trench;
the second high-k dielectric material is included in a second layer of the hybrid gate dielectric that is disposed on the first layer of the hybrid gate dielectric; and
the third high-k dielectric material is included in a third layer of the hybrid gate dielectric that is disposed on the second layer of the hybrid gate dielectric.
7. The power semiconductor device of claim 1 , wherein the hybrid gate dielectric further includes a third high-k dielectric material, the first high-k dielectric material and the third high-k dielectric material are a same high-k dielectric material.
8. The power semiconductor device of claim 1 , wherein the hybrid gate dielectric further includes a third high-k dielectric material, the hybrid gate dielectric includes a composite of the first high-k dielectric material, the second high-k dielectric material and the third high-k dielectric material.
9. The power semiconductor device of claim 8 , wherein respective concentrations of the first high-k dielectric material, the second high-k dielectric material and the third high-k dielectric material vary across a thickness of the hybrid gate dielectric.
10. The power semiconductor device of claim 1 , wherein the conductive gate electrode includes at least one of doped polysilicon, a metal and a silicide.
11. The power semiconductor device of claim 1 , further comprising a dielectric cap disposed on the conductive gate electrode.
12. The power semiconductor device of claim 1 , further comprising:
a heavy body region of the second conductivity type disposed in the well region and adjacent to the source region, the heavy body region having a doping concentration that is greater than a doping concentration of the well region.
13. A method comprising:
forming a SiC epitaxial layer of a first conductivity type on a SiC substrate of the first conductivity type, the SiC epitaxial layer having a doping concentration that is different than a doping concentration of the SiC substrate;
forming a well region of a second conductivity type in the SiC epitaxial layer;
forming a source region of the first conductivity type in the well region;
forming a gate trench in the SiC epitaxial layer and adjacent to the source region, the gate trench having a depth that is greater than a depth of the well region and that is less than a depth of the SiC epitaxial layer;
forming a gate dielectric structure on a sidewall of the gate trench and a bottom surface of the gate trench, the gate dielectric structure including:
a hybrid gate dielectric including a first high-k dielectric material and a second high-k dielectric material that is different than the first high-k dielectric material; and
an interface dielectric layer disposed between the hybrid gate dielectric and the SiC epitaxial layer, the interface dielectric layer including a thermally grown silicon dioxide (SiO 2 ) layer that fully separates the hybrid gate dielectric from the SiC epitaxial layer; and
forming a conductive gate electrode disposed on the hybrid gate dielectric.
14. The method of claim 13 , wherein the hybrid gate dielectric includes a composite of the first high-k dielectric material and the second high-k dielectric material.
15. The method of claim 14 , wherein respective concentrations of the first high-k dielectric material and the second high-k dielectric material vary across a thickness of the hybrid gate dielectric.
16. The method of claim 13 , wherein the hybrid gate dielectric further includes a third high-k dielectric material.