IP Library Granted Patent US 10,403,538
Granted Patent B2
US 10,403,538 · App. 15/983,158 · Granted Sep 3, 2019

Expansion method, method for manufacturing semiconductor device, and semiconductor device

Inventors: Yukihiro Iwanaga (Chiba, JP); Kouji Suzumura (Ichihara, JP); Tatsuya Sakuta (Ichihara, JP)
Assignee: HITACHI CHEMICAL COMPANY, LTD.
H01L21/6836H01L21/68H01L21/78H01L24/27H01L24/29H01L24/32H01L24/81H01L2221/68327H01L2221/68336H01L2221/68377H01L2221/68381H01L2224/2919H01L2224/32225H01L2224/32245H01L2224/48225H01L2224/48245H01L2224/73265H01L2224/83191H01L2224/83862H01L2224/94
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Quick Facts
Patent No.
US 10,403,538
App. No.
15/983,158
Granted
Sep 3, 2019
Kind
B2
Abstract

An embodiment of the present invention relates to an expansion method comprising: a step (I) of preparing a laminate having a semiconductor wafer in which modified sections have been formed along intended cutting lines, a die bonding film and a dicing tape, a step (IIA) of expanding the dicing tape with the laminate in a cooled state, a step (IIB) of loosening the expanded dicing tape, and a step (IIC) of expanding the dicing tape with the laminate in a cooled state, dividing the semiconductor wafer and the die bonding film into chips along the intended cutting lines, and widening the spaces between the chips.

Claims (51)

1. An expansion method comprising:

a step (la) of preparing a laminate having a semiconductor wafer, a die bonding film, a dicing tape and a frame, the semiconductor wafer comprising modified sections formed along intended cutting lines, the modified sections comprising melt treatment regions formed by localized heating and melting of the interior of the semiconductor wafer,

a step (Ib) of supplying the laminate to a height-adjustable expansion stage of an expansion apparatus comprising the expansion stage and a fastening member capable of fastening the frame,

a step (Ic) of fastening the frame using the fastening member,

a step (IIa) of raising the expansion stage and expanding the dicing tape with the laminate in a cooled state,

a step (IIb) of lowering the raised expansion stage and loosening the expanded dicing tape, and

a step (IIc) of raising the expansion stage and expanding the dicing tape with the laminate in a cooled state, dividing the semiconductor wafer and the die bonding film into chips along the intended cutting lines, and widening spaces between the chips.

2. An expansion method comprising:

a step (Ia′) of preparing a laminate having a semiconductor wafer, a die bonding film, a dicing tape and a frame, the semiconductor wafer comprising modified sections formed along intended cutting lines, the modified sections comprising melt treatment regions formed by localized heating and melting of the interior of the semiconductor wafer,

a step (Ib′) of supplying the laminate to a height-adjustable expansion ring of an expansion apparatus comprising the expansion ring and a fastening member capable of fastening the frame,

a step (Ic′) of fastening the frame using the fastening member,

a step (IIa′) of raising the expansion ring and expanding the dicing tape with the laminate in a cooled state,

a step (IIb′) of lowering the raised expansion ring and loosening the expanded dicing tape, and

a step (IIc′) of raising the expansion ring and expanding the dicing tape with the laminate in a cooled state, dividing the semiconductor wafer and the die bonding film into chips along the intended cutting lines, and widening spaces between the chips.

3. The expansion method according to claim 1 , wherein an external force applied to the dicing tape by the expansion stage in the step (IIc) is greater than an external force applied to the dicing tape by the expansion stage in the step (IIa).

4. A method for manufacturing a semiconductor device comprising:

a step (I) of preparing a laminate having a semiconductor wafer, a die bonding film, a dicing tape and a frame,

a step (II) of expanding the dicing tape, dividing the semiconductor wafer and the die bonding film into chips along the intended cutting lines, and widening spaces between the chips,

a step (III) of picking up a chip from the dicing tape,

and a step (IV) of die bonding the chip to an adherend, wherein

the step (I) and the step (II) are performed using the expansion method according to claim 1 .

5. A semiconductor device having an adherend, and a chip bonded to the adherend, wherein the semiconductor device is manufactured using the method for manufacturing a semiconductor device according to claim 4 .

6. The expansion method according to claim 2 , wherein an external force applied to the dicing tape by the expansion ring in the step (IIc′) is greater than an external force applied to the dicing tape by the expansion ring in the step (IIa′).

7. A method for manufacturing a semiconductor device comprising:

a step (I) of preparing a laminate having a semiconductor wafer, a die bonding film, a dicing tape and a frame,

a step (II) of expanding the dicing tape, dividing the semiconductor wafer and the die bonding film into chips along the intended cutting lines, and widening spaces between the chips,

a step (III) of picking up a chip from the dicing tape,

and a step (IV) of die bonding the chip to an adherend, wherein

the step (I) and the step (II) are performed using the expansion method according to claim 2 .

8. A semiconductor device having an adherend, and a chip bonded to the adherend, wherein the semiconductor device is manufactured using the method for manufacturing a semiconductor device according to claim 7 .

9. The method of claim 1 , wherein the loosening of the expanded dicing tape in step (IIb) occurs for not more than 10 seconds.

10. The method of claim 2 , wherein the loosening of the expanded dicing tape in step (IIb′) occurs for not more than 10 seconds.

11. The method of claim 1 , further comprising forming the modified sections in the semiconductor wafer before preparing the laminate.

12. The method of claim 2 , further comprising forming the modified sections in the semiconductor wafer before preparing the laminate.

13. An expansion method comprising at least one method selected form the group consisting of a method (i) and a method (ii), wherein

the method (i) comprises:

a step (Ia) of preparing a laminate having a semiconductor wafer, a die bonding film, a dicing tape and a frame, the semiconductor wafer comprising dicing lines along intended cutting lines,

a step (Ib) of supplying the laminate to a height-adjustable expansion stage of an expansion apparatus comprising the expansion stage and a fastening member capable of fastening the frame,

a step (Ic) of fastening the frame using the fastening member,

a step (IIa) of raising the expansion stage and expanding the dicing tape with the laminate in a cooled state,

a step (IIb) of lowering the raised expansion stage and loosening the expanded dicing tape, and

a step (IIc) of raising the expansion stage and expanding the dicing tape with the laminate in a cooled state, dividing the semiconductor wafer and the die bonding film into chips along the intended cutting lines, and widening spaces between the chips,

wherein the dicing lines are configured to be cut by performing the steps (Ib) to (IIc), and

the method (ii) comprises:

a step (Ia′) of preparing a laminate having a semiconductor wafer, a die bonding film, a dicing tape and a frame, the semiconductor wafer comprising dicing lines along intended cutting lines,

a step (Ib′) of supplying the laminate to a height-adjustable expansion ring of an expansion apparatus comprising the expansion ring and a fastening member capable of fastening the frame,

a step (Ic′) of fastening the frame using the fastening member,

a step (IIa′) of raising the expansion ring and expanding the dicing tape with the laminate in a cooled state,

a step (IIb′) of lowering the raised expansion ring and loosening the expanded dicing tape, and

a step (IIc′) of raising the expansion ring and expanding the dicing tape with the laminate in a cooled state, dividing the semiconductor wafer and the die bonding film into chips along the intended cutting lines, and widening spaces between the chips,

wherein the dicing lines are configured to be cut by performing the steps (Ib′) to (IIc′).

Assignments (4)
CHANGE OF ADDRESS Recorded Feb 14, 2024
From: RESONAC CORPORATION
To: RESONAC CORPORATION
Reel/Frame 066599/0037 →
CHANGE OF NAME Recorded Mar 3, 2023
From: SHOWA DENKO MATERIALS CO., LTD.
To: RESONAC CORPORATION
Reel/Frame 062946/0125 →
CHANGE OF NAME Recorded Mar 2, 2023
From: HITACHI CHEMICAL COMPANY, LTD.
To: SHOWA DENKO MATERIALS CO., LTD.
Reel/Frame 062917/0865 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 18, 2018
From: IWANAGA, YUKIHIRO; SUZUMURA, KOUJI; SAKUTA, TATSUYA
To: HITACHI CHEMICAL COMPANY, LTD.
Reel/Frame 045843/0223 →
Priority Claims (1)
JP 2012-282785 · Dec 26, 2012 · national
Continuity (2)
Continuation 14655079
Related Publication 20180323097A1 · Nov 8, 2018
Cited By (1)
US 12,347,733