Low dropout regulator and method for controlling the same

1. A low dropout regulator, comprising a control circuit, a digital regulator circuit, and an analog regulator circuit,

wherein the control circuit is communicatively connected to an output terminal of the low dropout regulator and is configured to:

receive an output voltage output by the output terminal, a first threshold voltage, a second threshold voltage, and a reference voltage;

compare the output voltage with the first threshold voltage and compare the output voltage with the second threshold voltage;

generate a first control signal in a state where the output voltage is less than the first threshold voltage or greater than the second threshold voltage; and

generate a second control signal in a state where the output voltage is greater than the first threshold voltage and less than the second threshold voltage,

wherein the digital regulator circuit is communicatively connected to the control circuit and is configured to:

adjust the output voltage according to the first control signal so that the output voltage is equal to the reference voltage; and

maintain the output voltage according to the second control signal,

wherein the analog regulator circuit is communicatively connected to the control circuit and is configured to:

output feedback current to the output terminal according to the output voltage and the reference voltage under the trigger of the second control signal to reduce an output ripple, and

wherein the reference voltage is greater than the first threshold voltage, and the reference voltage is less than the second threshold voltage.

2. The low dropout regulator according to claim 1 , wherein the control circuit comprises a comparison circuit, an encoding circuit, a clock frequency control circuit, a plurality of switches, and a switch control circuit configured to control the plurality of switches,

wherein the comparison circuit is communicatively connected to the output terminal of the low dropout regulator and is configured to:

compare the output voltage with the first threshold voltage;

compare the output voltage with the second threshold voltage;

compare the output voltage with the reference voltage; and

output comparison results to the encoding circuit,

wherein the encoding circuit is communicatively connected to the comparison circuit and is configured to:

output a first code in a state where the output voltage is less than the first threshold voltage or greater than the second threshold voltage; and

output a second code in a state where the output voltage is greater than the first threshold voltage and less than the second threshold voltage,

wherein the clock frequency control circuit is communicatively connected to the encoding circuit and is configured to:

generate a high frequency clock signal according to the first code; and

generate an intermediate frequency clock signal according to the second code,

wherein the switch control circuit is communicatively connected to the encoding circuit and is configured to:

generate a first signal for controlling all the plurality of switches to be turned off according to the first code; and

generate a second signal for controlling all the plurality of switches to be turned on according to the second code,

wherein the plurality of switches are connected to the analog regulator circuit; and

wherein the first control signal comprises the high frequency clock signal and the first signal, and the second control signal comprises the intermediate frequency clock signal and the second signal.

3. The low dropout regulator according to claim 2 , wherein the comparison circuit comprises a first comparator, a second comparator, and a third comparator,

wherein the first comparator has a positive input terminal configured to input the first threshold voltage, and a negative input terminal configured to input the output voltage output by the output terminal;

wherein the second comparator has a positive input terminal configured to input the reference voltage, and a negative input terminal configured to input the output voltage output by the output terminal; and

wherein the third comparator has a positive input terminal configured to input the second threshold voltage, and a negative input terminal configured to input the output voltage output by the output terminal.

4. The low dropout regulator according to claim 2 , wherein the digital regulator circuit comprises a counting circuit, a decoding circuit, and an array of transistors,

wherein the counting circuit is communicatively connected to the comparison circuit and is configured to generate a third control signal according to the comparison result of the comparison circuit and the high frequency clock signal, and

wherein the decoding circuit is communicatively connected to the counting circuit and is configured to control a number of transistors to be turned on in the array of transistors according to the third control signal.

5. The low dropout regulator according to claim 4 , wherein the transistors in the array of transistors comprise P-channel metal oxide semiconductor transistors, and/or N-channel metal oxide semiconductor transistors, and/or thin film transistors.

6. The low dropout regulator according to claim 4 , further comprising: a feedback resistor network and a capacitor,

wherein the feedback resistor network has a first terminal connected to the output terminal of the low dropout regulator, and a second terminal connected to the ground, and is configured to shunt current output by the output terminal of the low dropout regulator; and

wherein the capacitor has a first terminal connected to the output terminal of the low dropout regulator, and a second end connected to the ground, and is configured to regulate the voltage output by the output terminal of the low dropout regulator.

7. The low dropout regulator according to claim 2 , wherein the analog regulator circuit comprises an amplifying circuit and a power transistor,

wherein the amplifying circuit has a positive input terminal configured to input the reference voltage, and a negative input terminal configured to input the output voltage output by the output terminal, and is configured to amplify the reference voltage and the output voltage, and

wherein the power transistor is communicatively connected to the amplifying circuit and is configured to generate the feedback current according to the amplified reference voltage and the amplified output voltage.

8. A method for controlling a low dropout regulator of claim 1 , the method comprising:

receiving an output voltage output by the output terminal of the low dropout regulator, a first threshold voltage, a second threshold voltage, and a reference voltage;

comparing the output voltage with the first threshold voltage and comparing the output voltage with the second threshold voltage;

generating a first control signal in a state where the output voltage is less than the first threshold voltage or greater than the second threshold voltage;

adjusting the output voltage according to the first control signal so that the output voltage is equal to the reference voltage;

generating a second control signal in a state where the output voltage is greater than the first threshold voltage and less than the second threshold voltage;

maintaining the output voltage according to the second control signal; and

outputting feedback current to the output terminal according to the output voltage and the reference voltage under the trigger of the second control signal to reduce an output ripple;

wherein the reference voltage is greater than the first threshold voltage, and the reference voltage is less than the second threshold voltage.

9. The method according to claim 8 ,

wherein generating a first control signal in a state where the output voltage is less than the first threshold voltage or greater than the second threshold voltage comprises:

outputting a first code in a state where the output voltage is less than the first threshold voltage or greater than the second threshold voltage; and

generating a first control signal comprising a high frequency clock signal and a first signal for controlling all the plurality of switches to be turned off according to the first code, and

wherein adjusting the output voltage according to the first control signal comprises:

generating a third control signal according to a comparison result of the comparison circuit and the high frequency clock signal; and

controlling a number of transistors to be turned on in the array of transistors according to the third control signal.

10. The method according to claim 8 ,

wherein generating a second control signal in a state where the output voltage is greater than the first threshold voltage and less than the second threshold voltage comprises:

outputting a second code in a state where the output voltage is greater than the first threshold voltage and less than the second threshold voltage; and

generating the second control signal comprising an intermediate frequency clock signal and a second signal for controlling all the plurality of switches to be turned on according to the second code,

wherein maintaining the output voltage according to the second control signal comprises:

maintaining the output voltage according to the intermediate frequency clock signal; and

wherein outputting feedback current to the output terminal according to the output voltage and the reference voltage comprises:

amplifying the reference voltage and the output voltage; and

generating the feedback current according to the amplified reference voltage and the amplified output voltage.