Digital low dropout regulator for generating output voltage dependent on DAC code signal
A digital low dropout regulator (LDO) for receiving a reference voltage and generating an output voltage, the digital LDO being synchronized to a clock signal and comprising a first digital to analog converter configured to generate a first DAC code signal, the output voltage being dependent the first DAC code signal, trigger state transitions of the first DAC code signal between states, and for at least a portion of the state transitions of the first DAC code signal, trigger each subsequent state transition after more clock cycles of the clock signal than for the preceding state transition.
1 . A digital low dropout regulator (LDO) for receiving a reference voltage and generating an output voltage, the digital LDO being synchronized to a clock signal and comprising:
a first digital to analog converter configured to:
generate a first DAC code signal, the output voltage being dependent the first DAC code signal;
trigger state transitions of the first DAC code signal between states, the state transitions comprising rising transitions and/or falling transitions;
trigger a first rising transition after n clock cycles, where n is a positive integer, and trigger a second rising transition after the first rising transition and after m clock cycles, where m is an integer and greater than n; and/or
trigger a first falling transition after p clock cycles, where p is a positive integer, and trigger a second falling transition after the first falling transition and after q clock cycles, where q is an integer and greater than p.
2 . The digital LDO of claim 1 comprising:
a comparison circuit configured to:
receive the reference voltage;
receive a feedback voltage, the feedback voltage being dependent on the output voltage;
compare the reference voltage and the feedback voltage; and
generate an error signal that is dependent on the comparison between the reference voltage and the feedback voltage,
wherein the first digital to analog converter is configured to:
receive the error signal; and
generate the first DAC code signal based on the error signal.
3 . The digital LDO of claim 2 , wherein the first digital to analog converter comprises a first shift register configured to generate the first DAC code signal.
4 . The digital LDO of claim 3 , wherein the first shift register comprises an up-down counter.
5 . The digital LDO of claim 3 , wherein the first digital to analog converter comprises a plurality of first current sources, and each of the first current source functions as a bit of the first DAC code signal.
6 . The digital LDO of claim 5 , wherein each of the first current sources comprises a first transistor of a plurality of first transistors.
7 . The digital LDO of claim 6 , wherein the first shift register comprises a plurality of outputs, each output being associated with a single bit of the first DAC code signal and coupled to a gate of one of the plurality of first transistors.
8 . The digital LDO of claim 7 , wherein the first digital to analog converter comprises a plurality of first buffer circuits, each output being coupled to the gate of one of the plurality of first transistors via a buffer circuit.
9 . The digital LDO of claim 8 , each of the first buffer circuits comprises a first inverter.
10 . The digital LDO of claim 9 , comprising an output capacitor having an equivalent series resistance, the first DAC signal being provided to the output capacitor to generate the output voltage.
11 . The digital LDO of claim 1 , wherein n and p are equal and/or m and q are equal.
12 . The digital LDO of claim 1 , wherein the digital LDO comprises a second digital to analog converter configured to generate a second DAC code signal, the output voltage being dependent on the second DAC code signal.
13 . The digital LDO of claim 12 , wherein the first digital to analog converter is configured to provide fine control of the output voltage and the second digital to analog converter is configured to provide coarse control of the output voltage.
14 . The digital LDO of claim 12 , comprising:
a comparison circuit configured to:
receive the reference voltage;
receive a feedback voltage, the feedback voltage being dependent on the output voltage;
compare the reference voltage and the feedback voltage; and
generate an error signal that is dependent on the comparison between the reference voltage and the feedback voltage,
wherein the first digital to analog converter is configured to:
receive the error signal; and
generate the first DAC code signal based on the error signal, and
wherein the second digital to analog converter is configured to:
receive the error signal; and
generate the second DAC code signal based on the error signal.
15 . The digital LDO of claim 2 , comprising a clock circuit configured to generate the clock signal.
16 . The digital LDO of claim 15 comprising:
a panic circuit configured to:
detect when the feedback voltage exceeds a first threshold voltage value or falls below a second threshold voltage value; and
control the first digital to analog converter to operate in a panic mode when the feedback voltage exceeds the first threshold voltage value or falls below the second threshold voltage value,
wherein the clock circuit is configured to:
provide the clock signal to the comparison circuit;
operate in a fast mode during the panic mode by providing the clock signal at a first frequency; and
operate in a slow mode, when not in the panic mode, by providing the clock signal at a second frequency, the second frequency being less than the first frequency.
17 . A method of generating an output voltage using a digital LDO comprising a first digital to analog converter and synchronized to a clock signal comprising:
receiving a reference voltage at the digital LDO;
generating a first DAC code signal using the first digital to analog converter;
triggering state transitions of the first DAC code signal between states using the first digital to analog converter, the state transitions comprising rising transitions and/or falling transitions;
triggering a first rising transition after n clock cycles, where n is a positive integer, and triggering a second rising transition after the first rising transition and after m clock cycles, where m is an integer and greater than n; and/or
triggering a first falling transition after p clock cycles, where p is a positive integer, and triggering a second falling transition after the first falling transition and after q clock cycles, where q is an integer and greater than p; and nverter; and
generating the output voltage, the output voltage being dependent on the first DAC code signal.