Magnetic memory emulating dynamic random access memory (DRAM)
View Patent ↗The present invention is directed to a magnetic memory device comprising a memory array structure that includes a first memory array comprising a first plurality of memory cells and a second memory array comprising a second plurality of memory cells. Each memory cell of the first and second plurality of magnetic memory cells includes a magnetic memory element and a two-terminal selector coupled in series. The memory array structure further includes a first multiplexer coupled to a third plurality of first conductive lines with each line connected to a respective column of the first plurality of memory cells; a second multiplexer coupled to a fourth plurality of first conductive lines with each line connected to a respective column of the second plurality of memory cells; a sense amplifier, whose input is connected to the output of the first multiplexer and the output of the second multiplexer; and one or more latches coupled to the sense amplifier.
1. A method for reading a data bit stored in a magnetic memory array that includes multiple magnetic memory sub-arrays, each of which including a plurality of magnetic memory cells arranged in rows and columns with each of said plurality of magnetic memory cells including a magnetic memory element and a two-terminal selector coupled in series, a plurality of word lines coupled to said plurality of magnetic memory cells along a row direction, and a plurality of bit lines coupled to said plurality of magnetic memory cells along a column direction and sharing a sense amplifier through a multiplexer, said multiple magnetic memory sub-arrays being skewered together along said row direction by said plurality of word lines, the method comprising the steps of:
raising potential of a selected word line among said plurality of word lines to a first voltage, said selected word line connected to a selected magnetic memory cell for sensing;
turning on selectors of all magnetic memory cells connected to said selected word line, thereby activating a row of magnetic memory cells across all magnetic memory sub-arrays for sensing;
consecutively sensing activated magnetic memory cells within each magnetic memory sub-array by said sense amplifier and latching sensed data bits in a group of latches, said sensed data bits in said group of latches of each magnetic memory sub-array collectively form a page of data bits; and
selecting a data bit corresponding to said selected magnetic memory cell from said page of data bits and outputting said data bit corresponding to said selected magnetic memory cell to an input/output bus.
2. The method of claim 1 , wherein said first voltage is higher than a threshold voltage for said selector to turn on.
3. The method of claim 1 further including lowering said potential of said selected word line from said first voltage to a second voltage after the step of turning on selectors.
4. The method of claim 3 , wherein said second voltage is lower than a threshold voltage for said selector to turn on.
5. The method of claim 1 , wherein potential of word lines not connected to said selected magnetic memory cell and all bit lines are maintained at 0 V.
6. The method of claim 1 , wherein the step of selecting a data bit is carried out by a column address select (CAS).