Fan-out semiconductor package

1. A fan-out semiconductor package comprising:

a frame including a plurality of insulating layers, a plurality of wiring layers disposed on the plurality of insulating layers, and a plurality of connection via layers penetrating through the plurality of insulating layers and electrically connecting the plurality of wiring layers to each other, and having a recess portion having a stopper layer disposed on a bottom surface thereof;

a semiconductor chip having connection pads, an active surface on which the connection pads are disposed, and an inactive surface opposing the active surface, and being disposed in the recess portion so that the inactive surface is connected to the stopper layer;

an encapsulant covering at least portions of the semiconductor chip and filling at least portions of the recess portion; and

a connection member disposed on the frame and the active surface of the semiconductor chip and including a redistribution layer electrically connecting the plurality of wiring layers of the frame and the connection pads of the semiconductor chip to each other,

wherein the stopper layer includes an insulating material,

wherein the plurality of insulating layers including a core insulating layer and one or more first build-up insulating layers disposed on an upper surface of the core insulating layer, and

wherein the recess portion penetrates through the core insulating layer and a first build-up insulating layer from among the one or more first build-up insulating layers.

2. The fan-out semiconductor package of claim 1 , wherein the insulating material of the stopper layer includes a photosensitive polymer.

3. The fan-out semiconductor package of claim 1 , wherein the stopper layer is a dry film photo-resist (DFR).

4. The fan-out semiconductor package of claim 1 , wherein the plurality of insulating layers include one or more second build-up insulating layers disposed below of the core insulating layer, and

the core insulating layer has a thickness greater than that of each of the first and second build-up insulating layers.

5. The fan-out semiconductor package of claim 4 , wherein the number of first build-up insulating layers and the number of second build-up insulating layers are the same as each other.

6. The fan-out semiconductor package of claim 4 , wherein first connection vias penetrating through the first build-up insulating layer and second connection vias penetrating through the second build-up insulating layer are tapered in opposite directions to each other.

7. The fan-out semiconductor package of claim 4 , wherein the recess portion penetrates through at least the core insulating layer, and

walls of the recess portion penetrating through the core insulating layer are tapered to have a first gradient.

8. The fan-out semiconductor package of claim 7 , wherein

a guide layer of which side surfaces are exposed through the recess portion is disposed on the upper surface of the core insulating layer, and

walls of the recess portion penetrating through the first build-up insulating layer are tapered to have a second gradient different from the first gradient.

9. The fan-out semiconductor package of claim 8 , wherein an insulating material of the guide layer includes a photosensitive polymer.

10. The fan-out semiconductor package of claim 8 , wherein the guide layer is a DFR.

11. The fan-out semiconductor package of claim 8 , wherein the walls of the recess portion are tapered in opposite directions to each other in relation to the exposed side surfaces of the guide layer.

12. The fan-out semiconductor package of claim 1 , wherein a region of the stopper layer exposed by the recess portion has a thickness smaller than that of an edge region of the stopper layer that is not exposed.

13. The fan-out semiconductor package of claim 1 , wherein the stopper layer has a planar area greater than that of the inactive surface of the semiconductor chip.

14. The fan-out semiconductor package of claim 1 , wherein the bottom surface of the recess portion has a planar area greater than that of the inactive surface of the semiconductor chip.

15. The fan-out semiconductor package of claim 1 , wherein a lowermost wiring layer of the plurality of wiring layers is embedded in the frame so that a lower surface thereof is exposed.

16. The fan-out semiconductor package of claim 15 , wherein the exposed lower surface of the lowermost wiring layer has a step with respect to a lower surface of the frame.

17. The fan-out semiconductor package of claim 1 , wherein the inactive surface of the semiconductor chip is attached to the stopper layer by an adhesive member.

18. The fan-out semiconductor package of claim 1 , wherein metal bumps are disposed on the connection pads of the semiconductor chip, and

upper surfaces of the metal bumps are coplanar with an upper surface of the encapsulant.

19. The fan-out semiconductor package of claim 18 , wherein an upper surface of an uppermost wiring layer of the plurality of wiring layers of the frame or an upper surface of an uppermost connection via layer of the plurality of connection via layers is coplanar with the upper surfaces of the metal bumps and the upper surface of the encapsulant.

20. The fan-out semiconductor package of claim 1 , further comprising: a first passivation layer disposed on the connection member and having openings exposing at least portions of the redistribution layer;

underbump metal layers disposed in the openings of the first passivation layer and connected to at least portions of the exposed redistribution layer; and

electrical connection structures disposed on the first passivation layer and connected to the underbump metal layers.

21. The fan-out semiconductor package of claim 20 , further comprising a second passivation layer disposed below of the frame and having openings exposing at least portions of a lowermost wiring layer of the plurality of wiring layers.

22. The fan-out semiconductor package of claim 1 , wherein at least one of the wiring layers are disposed on a level below the stopper layer.

23. A fan-out semiconductor package, comprising:

a frame having a recess having a stopper layer disposed on a bottom surface of the recess, and having wiring layers disposed on each of an upper and a lower surface of the frame;

a semiconductor chip having an active surface and an inactive surface and being disposed in the recess such that the inactive surface contacts the stopper layer, the active surface comprising connection pads; and

an encapsulant covering at least portions of the frame, the semiconductor chip, and filling at least a portion of the recess,

wherein the frame includes a core insulating layer and one or more build-up insulating layers disposed on an upper surface of the core insulating layer, and

wherein the recess portion penetrates through the core insulating layer and a build-up insulating layer from among the one or more build-up insulating layers.

24. The fan-out semiconductor package of claim 23 , wherein metal bumps are disposed on the connection pads of the semiconductor chip, and

upper surfaces of the metal bumps are coplanar with an upper surface of the encapsulant.

25. The fan-out semiconductor package of claim 24 , further comprising a connection member disposed on the frame and the active surface of the semiconductor chip, the connection member comprising a redistribution layer electrically connected to the connection pads and the uppermost wiring layer through the metal bumps.

26. The fan-out semiconductor package of claim 23 , wherein the stopper layer comprises an insulating material having an etching rate lower than that of copper (Cu) in a sandblasting process.