Memory disturb detection
An apparatus includes an array of memory cells comprising a first sub-block and a second sub-block electrically coupled by a channel. The apparatus also includes a measurement circuit configured to take a first measurement of a first sub-block of memory cells at a first offset threshold and a second measurement of the first sub-block of memory cells at a second offset threshold. The apparatus further includes a detection circuit configured to detect a disturb condition of the first sub-block based on at least one of the first measurement and the second measurement, and to initiate data maintenance in response to the disturb condition of the first sub-block.
1. An apparatus, comprising:
an array of memory cells comprising a first sub-block and a second sub-block electrically coupled by a channel;
a measurement circuit configured to take a first measurement of the first sub-block of memory cells at a first offset threshold and a second measurement of the first sub-block of memory cells at a second offset threshold;
a detection circuit configured to detect a disturb condition of the first sub-block based on at least one of the first measurement or the second measurement; and
a write circuit configured to send a compensating pulse in response to the detection circuit detecting the disturb condition of the first sub-block in order to counter a change in an electric characteristic of the first sub-block away from a target level.
2. The apparatus of claim 1 , wherein the first offset threshold is offset below a read threshold and the second offset threshold is offset above the read threshold.
3. The apparatus of claim 1 , wherein:
the measurement circuit is configured to utilize the first measurement and the second measurement to determine a cell count within a range between the first offset threshold and the second offset threshold; and
the detection circuit is configured to detect the disturb condition of the first sub-block in response to the cell count satisfying a cell count threshold.
4. The apparatus of claim 1 , wherein the disturb condition is indicated by a check failure of one or more of the first measurement or the second measurement.
5. The apparatus of claim 1 , wherein when the disturb condition of the first sub-block comprises a program disturb, the compensating pulse sent by the write circuit comprises a compensating erase pulse.
6. The apparatus of claim 5 , wherein the compensating erase pulse has a lower amplitude in comparison with a normal erase pulse in order to shift a threshold voltage downward by an amount without completely erasing one or more memory cells of the first sub-block.
7. The apparatus of claim 1 , wherein when the disturb condition of the first sub-block comprises a program disturb, the compensating pulse sent by the write circuit comprises a compensating program pulse.
8. The apparatus of claim 7 , wherein the compensating program pulse has a lower amplitude in comparison with a normal program pulse in order to shift a threshold voltage upward by an amount without increasing the threshold voltage of one or more memory cells of the first sub-block beyond a target threshold voltage level.
9. An apparatus, comprising:
an array of memory cells comprising a first sub-block and a second sub-block electrically coupled by a channel;
one or more circuits configured to
take a first measurement of the first sub-block of memory cells at a first offset threshold and a second measurement of the first sub-block of memory cells at a second offset threshold,
detect a disturb condition of the first sub-block based on at least one of the first measurement or the second measurement, and
send a compensating pulse, in response to the disturb condition of the first sub-block being detected, in order to counter a change in an electric characteristic of the first sub-block away from a target level.
10. The apparatus of claim 9 , wherein the first offset threshold is offset below a read threshold and the second offset threshold is offset above the read threshold.
11. The apparatus of claim 9 , wherein the one or more circuits are configured to:
utilize the first measurement and the second measurement to determine a cell count within a range between the first offset threshold and the second offset threshold; and
detect the disturb condition of the first sub-block in response to the cell count satisfying a cell count threshold.
12. The apparatus of claim 9 , wherein the disturb condition is indicated by a check failure of one or more of the first measurement or the second measurement.
13. The apparatus of claim 9 , wherein when the disturb condition of the first sub-block comprises a program disturb, the compensating pulse that is sent comprises a compensating erase pulse.
14. The apparatus of claim 13 , wherein the compensating erase pulse has a lower amplitude in comparison with a normal erase pulse in order to shift a threshold voltage downward by an amount without completely erasing one or more memory cells of the first sub-block.
15. The apparatus of claim 9 , wherein when the disturb condition of the first sub-block comprises a program disturb, the compensating pulse that is sent comprises a compensating program pulse.
16. The apparatus of claim 15 , wherein the compensating program pulse has a lower amplitude in comparison with a normal program pulse in order to shift a threshold voltage upward by an amount without increasing the threshold voltage of one or more memory cells of the first sub-block beyond a target threshold voltage level.
17. A method, comprising:
taking a first measurement of a first sub-block of memory cells at a first offset threshold and taking a second measurement of the first sub-block of memory cells at a second offset threshold, wherein the first sub-block of memory cells are included within an array of memory cells that also includes a second sub-block of memory cells that is coupled to the first sub-block by a channel;
detecting a disturb condition of the first sub-block based on at least one of the first measurement or the second measurement; and
sending a compensating pulse in response to the detecting the disturb condition of the first sub-block in order to counter a change in an electric characteristic of the first sub-block away from a target level.
18. The method of claim 17 , wherein the first offset threshold is offset below a read threshold and the second offset threshold is offset above the read threshold.
19. The method of claim 17 , wherein the detecting the disturb condition comprises:
utilizing the first measurement and the second measurement to determine a cell count within a range between the first offset threshold and the second offset threshold; and
detecting the disturb condition of the first sub-block in response to the cell count satisfying a cell count threshold.
20. The method of claim 17 , wherein the disturb condition is indicated by a check failure of one or more of the first measurement or the second measurement.
21. The method of claim 17 , wherein when the disturb condition of the first sub-block comprises a program disturb, the compensating pulse that is sent comprises a compensating program pulse.
22. The method of claim 21 , wherein the compensating program pulse has a lower amplitude in comparison with a normal program pulse in order to shift a threshold voltage upward by an amount without increasing the threshold voltage of one or more memory cells of the first sub-block beyond a target threshold voltage level.
23. The method of claim 17 , wherein when the disturb condition of the first sub-block comprises a program disturb, the compensating pulse that is sent comprises a compensating erase pulse.
24. The method of claim 23 , wherein the compensating erase pulse has a lower amplitude in comparison with a normal erase pulse in order to shift a threshold voltage downward by an amount without completely erasing one or more memory cells of the first sub-block.