Methods for processing a 3D semiconductor device
A method for processing a 3D semiconductor device, the method including: providing a wafer including a plurality of first dies, the plurality of first dies including a first transistor layer and a first interconnection layer; completing a step of transferring a plurality of second dies each overlaying at least one of the first dies, where each of the plurality of second dies includes a second transistor layer, where at least one of the plurality of first dies is substantially larger in area than at least one of the plurality of second dies, and where each of the plurality of second dies has a thickness greater than six microns; and completing a step of thinning the plurality of second dies, where each of the plurality of second dies has a thickness of less than 2 microns.
1. A method for processing a 3D semiconductor device, the method comprising:
providing a wafer comprising a plurality of first dies, said plurality of first dies comprising a first transistor layer and a first interconnection layer;
completing a step of transferring a plurality of second dies each overlaying at least one of said first dies,
wherein each of said plurality of second dies comprises a second transistor layer,
wherein at least one of said plurality of first dies is substantially larger in area than at least one of said plurality of second dies, and
wherein each of said plurality of second dies has a thickness greater than six microns; and
completing a step of thinning said plurality of second dies,
wherein each of said plurality of second dies has a thickness of less than 2 microns.
2. The method according to claim 1 ,
wherein said step of thinning utilizes an embedded cut layer, and
wherein said second dies each comprise said embedded cut layer prior to said completing a step of thinning.
3. The method according to claim 1 ,
wherein a thermal isolative layer is disposed between said first die and said second die, and
wherein said isolative layer has a thermal conductivity of less than 0.5 W/m-K.
4. The method according claim 1 ,
wherein said overlaying comprises a face-to-face (F2F) die orientation.
5. The method according claim 1 ,
wherein each of said plurality of second dies comprises a second interconnection layer.
6. The method according claim 1 ,
wherein said second die is a pre-tested die.
7. The method according to claim 1 ,
wherein at least one of said second dies is directly connected to at least one of said first dies, and said method further comprising:
attaching a third die to at least one of said first dies or at least one of said second dies,
wherein said third die is directly connected to said at least one of said first dies.
8. A method for processing a 3D semiconductor device, the method comprising:
providing a wafer comprising a plurality of first dies, said plurality of first dies comprising a first transistor layer and a first interconnection layer;
completing a step of transferring a plurality of second dies each overlaying at least one of said first dies,
wherein each of said plurality of second dies comprises a second transistor layer,
wherein at least one of said plurality of first dies is substantially larger in area than at least one of said plurality of second dies,
wherein said wafer has a diameter larger than 150 mm,
wherein said second die is smaller than 30 mm by 30 mm, and
wherein each of said plurality of second dies has a thickness greater than six microns; and
completing a step of thinning said plurality of second dies,
wherein each of said plurality of second dies has a thickness of less than 2 microns.
9. The method according to claim 8 ,
wherein said step of thinning utilizes an embedded cut layer, and
wherein said second dies each comprise said embedded cut layer prior to said completing a step of thinning.
10. The method according to claim 8 ,
wherein a thermal isolative layer is disposed between said first die and said second die, and
wherein said isolative layer has a thermal conductivity of less than 0.5 W/m-K.
11. The method according claim 8 ,
wherein at least one of said second dies is a memory die.
12. The method according claim 8 ,
wherein said overlaying comprises a face-to-face (F2F) die orientation.
13. The method according claim 8 ,
wherein each of said plurality of second dies comprises a second interconnection layer.
14. The method according claim 8 ,
wherein said second die is a pre-tested die.
15. The method according to claim 8 ,
wherein at least one of said second dies is directly connected to at least one of said first dies, and said method further comprising:
attaching a third die to at least one of said first dies or at least one of said second dies,
wherein said third die is directly connected to said at least one of said first dies.
16. A method for processing a 3D semiconductor device, the method comprising:
providing a wafer comprising a plurality of first dies, said plurality of first dies comprising a first transistor layer and a first interconnection layer; and
completing a step of transferring a plurality of second dies each overlaying at least one of said first dies,
wherein each of said plurality of second dies comprises a second transistor layer,
wherein at least one of said plurality of first dies is substantially larger in area than at least one of said plurality of second dies,
wherein each of said plurality of second dies has a thickness greater than six microns, and
wherein said wafer comprises a plurality of designated cavities, said designated cavities are designed for assisting placement of said second dies.
17. The method according to claim 16 , further comprising:
completing a step of thinning said plurality of second dies,
wherein each of said plurality of second dies has a thickness of less than 2 microns.
18. The method according to claim 16 ,
wherein at least one of said second dies comprises a cut layer embedded within said second dies, said cut layer is designed to support future thinning of said second dies.
19. The method according to claim 16 ,
wherein a thermal isolative layer is disposed between said first die and said second die, and
wherein said isolative layer has a thermal conductivity of less than 0.5 W/m-K.
20. The method according claim 16 ,
wherein said overlaying comprises a face-to-face (F2F) die orientation.